Noise Reduction Termination for RFI Induced Channel Resonance using Common-mode Choke and Differential Signal Balancer

Kameya, Masaaki; Gofuku, Eishi; Nakamura, Kazuyuki

doi:10.1109/icsj52620.2021.9648895

Cited by 2 publications

(1 citation statement)

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“…To overcome this problem, we have developed a new DSB-EIM (DSBE2) that has vertically stacked delay lines and bifilar coupled inductors to realize two noise rejection frequencies of 2.4 and 5.4 GHz in the smaller layout area than DSBE1. 30) As the extensions of the previous report, this paper explains the design of the stacked delay lines which can obtain desired delay time and two noise rejection poles compared to the horizontally extended delay lines like CMF-IPDs.…”

Section: Introductionmentioning

confidence: 91%

Differential signal balancer embedded in silicon LSI as smallest common-mode filter combined bifilar coupling inductors and stacked delay lines

Kameya

Gofuku

Nakamura

2022

Jpn. J. Appl. Phys.

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The new differential signal balancer embedded in the metal wiring layer of silicon LSI having increased wiring density and improved characteristics is developed. An internal delay line circuit is stacked vertically to obtain a larger delay time than the extended horizontally structure, and the two inductors for common-mode noise rejection are configured with a stacked bifilar winding structure to obtain higher effective coupling and lower parasitic resistance. Compared to the previous design, the common-mode rejection ratios (CMRR) at 2.4 GHz and 5.4 GHz have been improved by 4.0 dB and 4.6 dB in a smaller area of 120 × 230 μm2, respectively.

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Section: Introductionmentioning

confidence: 91%