Differential signal balancer embedded in silicon LSI as smallest common-mode filter combined bifilar coupling inductors and stacked delay lines

Abstract

The new differential signal balancer embedded in the metal wiring layer of silicon LSI having increased wiring density and improved characteristics is developed. An internal delay line circuit is stacked vertically to obtain a larger delay time than the extended horizontally structure, and the two inductors for common-mode noise rejection are configured with a stacked bifilar winding structure to obtain higher effective coupling and lower parasitic resistance. Compared to the previous design, the common-mode rejection ratios (CMRR) at 2.4 GHz and 5.4 GHz have been improved by 4.0 dB and 4.6 dB in a smaller area of 120 × 230 μm2, respectively.