Noise Optimization of Charge Amplifiers With MOS Input Transistors Operating in Moderate Inversion Region for Short Peaking Times

Abstract

The noise of a fast charge sensitive amplifier (CSA) with an input MOS transistor operating in the moderate inversion region is discussed. The MOS transistor operation in the moderate inversion region becomes especially important in multichannel readout systems where limited power dissipation is required. The ENC of a CSA followed by a fast shaper is usually dominated by the voltage noise of the input MOS transistor. We carried out noise minimization for such a CSA, searching for an optimum input transistor width. The analyses were made using a simplified EKV model and were compared to HSPICE simulations using a BSIM3v3 model. We considered several CMOS technology generations with minimum transistor gate length ranging from 0.13 m to 0.8 m. We studied the sensitivity of ENC to the input transistor width, and propose a simple formula to estimate the optimum transistor width, which is valid in a wide current density range.Index Terms-Charge sensitive amplifier, CMOS.

Measurements of Matching and Noise Performance of a Prototype Readout Chip in 40 nm CMOS Process for Hybrid Pixel Detectors

“…For these reasons, we decided to base our CSA A) Core of the CSA: Table I shows the dimensions of the selected folded cascode transistors M1-M5 and their simulated operating points (drain-source current , transconductance and output conductance ). In order to minimize the noise of the CSA stage, we undertook the following measures: -we designed the input transistor M1 according to the criterion of capacitive matching with the detector capacitance [26], [27], -we reduced the noise contribution from other folded cascode transistors, -we decided to keep the CSA feedback setting control as flexible as possible in order to optimize the operation with the high rate of input pulses and noise performance. It is worth noting that we avoided using devices with minimal channel length in order to prevent short channel effects [19].…”

23552-channel IC for single photon counting pixel detectors with 75 µm pitch, ENC of 89 e^− rms, 19 e^− rms offset spread and 3% rms gain spread

“…The architecture of the low noise charge amplifier is based on folded cascade with Krummenacher feedback circuits [5] like in the solution presented previously in [6]. The noise can be optimized by setting properly the input transistor dimensions according to the detector capacitance [7], however the operation range of the input transistor (weak or strong inversion) also has to be taken into consideration [8]. By tuning the time constant of the CSA feedback one can find a compromise between the low noise level and high count rate performance of the CSA.…”

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“…Therefore, M1 and M2 40 m 1 m , which work in a moderate inversion region, are sized according to the noise optimization proposed here [14], and M3-M10 are sized respecting (1), (3), and (4).…”