Noise minimization via deep submicron system-on-chip integration in megapixel CMOS imaging sensors

Abstract

Infrared sensor designers have long maximized S/N ratio by employing pixel-based amplification in conjunction with supplemental noise suppression. Instead, we suppress photodiode noise using novel SoC implementation with simple three transistor pixel; supporting SoC components include a feedback amplifier having elements distributed amongst the pixel and column buffer, a tapered reset clock waveform, and reset timing generator. The tapered reset method does not swell pixel area, compel processing of the correlated reset and signal values, or require additional memory. Integrated in a 2.1 M pixel imager developed for generating high definition television, random noise is ∼8e-at video rates to 225 MHz. Random noise of ∼30e-would otherwise he predicted for the 5 μm 5 μm pixels having 5.5 fF detector capacitance with negligible image lag. Minimum sensor S/N ratio is 52 dB with 1920 by 1080 progressive readout at 60 Hz, 72 Hz and 90 Hz. Fixed pattern noise is <2 DN via on-chip signal processing.