NoC router using STT-MRAM based hybrid buffers with error correction and limited flit retransmission

Majumder, Turbo; Shekhar, Vinay S.

doi:10.1109/iscas.2015.7169144

Cited by 6 publications

(3 citation statements)

References 14 publications

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“…In the paper [21] the MTJs were integrated with CMOS for high-density (over 100 Mb) Spintronic ("STT") memory-design. A "6T-STT MRAM" with 400 mW powers and 45 ns delay was formed in the paper [22] using "500 x" performance for 1 GB density and [23] presented an "MRAM" with 50 nm diameter. [24] applied a fast "gem 5" simulation on "MRAM" and "DRAM" and manifested that we can replace the other memories using magnetic-RAM to reduce power consumption up to '8%' and '27%' at the cost of '2x' the area with 10.4 ns time-delay.…”

Section: Related Workmentioning

confidence: 99%

A Multilayer High-Speed Magnetic-Tunnel-Junction Magneto-resistive RAM Structure with Read-Disturb-Detection Circuit by Using Nano-Electronics Quantum Dot Cellular Method

Roy*,

Sarkar,

Das

2019

IJITEE

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In this nano technical world the “Complementary MOS technology” can be replaced by using “Quantum Dot Cellular Automata” with reversible logical phenomenon to achieve a fault tolerant, low-cost nano electronics formation by feature size, latency and power consumption minimization. The memory is one of the most interesting part of research in this digital world. This paper represents an optimizing highfrequency (in THz) reversible design of a “Random Access Memory” which is simulated by using nano electronics ‘QCA’ simulator to get a better performance than “Complementary MOS technology” with high frequency (in THz), less occupied area and dissipated power. This paper also shows a highlyflexible magnetic quantum cell logic-design and MTJ logical representation which is used for non-volatile MRAM which is widely used in digital electronics world and as a part of aerospace and military device. A reversible nano electronics formation of the control logic to select the word-line and inputline of the MRAM also presented here. The reversible-logic can avoid the information-loss in memory device by zero-heating technique. Non-reversible formations dissipate ‘KTln2’ energy per bit which can be ignored in reversible formation. But, read disturb at low write current is a major issue of MTJ MRAM due to the same path of read/write current path. In this paper a three dimension reversible “Read Disturb Detection Circuit” is formed by nano electronics ‘QCA’ technology which bit-wise follows the control logic of read-disturb-detection technique and the same figure also simulated by ‘VHDL’ coding in Xilinx software to prove the advantages of ‘QCA’ technology contrast to Xilinx This paper also focuses on the correspondence between change of temperature and supply power.

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Section: Related Workmentioning

confidence: 99%

A Multilayer High-Speed Magnetic-Tunnel-Junction Magneto-resistive RAM Structure with Read-Disturb-Detection Circuit by Using Nano-Electronics Quantum Dot Cellular Method

Roy*,

Sarkar,

Das

2019

IJITEE

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“…Majumber, Suri and Shekhar [12] propose a hybrid buffer for cells of Static Random-Access Memory (SRAM) and Spin Transfer Torque-Magnetic RAM (STT-MRAM) with Single-Error Correct-Double Error Detection (SEC-DED) mechanism against transient faults. The proposal considers the buffer depth to minimize the performance impact since 4-bit cells of Single Event Effect-MRAM (SEE-MRAM) can replace an SRAM bit cell.…”

Section: Introductionmentioning

confidence: 99%

Optimized buffer protection for network-on-chip based on Error Correction Code

Pinheiro

Tavares

Silva

et al. 2020

Microelectronics Journal

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“…For example, crosstalk avoidance code schemes can avoid the chain transition affection between adjacent wires. The receiver router requires the retransmission of the flit if errors are detected [5]. However, it aggravates the burden of power consumption because the frequent encode/decode and retransmission operations cost additional power.…”

Section: Introductionmentioning

confidence: 99%

Reliable NoC design with low latency and power consumption

Yan

Gao

2017

Electron. lett.

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Reliability has become one of the most crucial issues in network-onchip (NoC). But how to keep low latency and power consumption when achieving reliability is still a curial challenge. A novel scheme for reliable NoCs is proposed. In the scheme, header flit is protected from router to router and data is protected from end to end. To implement the scheme, a new header protection buffer in routers is designed, which can check the timing errors and tolerate the soft errors simultaneously. Instead of checking on each router, data packet is only decoded and checked on receiver's network interface. In this way, the scheme ensures reliable transmission with low latency and power consumption. Experimental results show the feasibility of the proposed scheme in terms of power consumption, latency and area cost.

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NoC router using STT-MRAM based hybrid buffers with error correction and limited flit retransmission

Cited by 6 publications

References 14 publications

A Multilayer High-Speed Magnetic-Tunnel-Junction Magneto-resistive RAM Structure with Read-Disturb-Detection Circuit by Using Nano-Electronics Quantum Dot Cellular Method

A Multilayer High-Speed Magnetic-Tunnel-Junction Magneto-resistive RAM Structure with Read-Disturb-Detection Circuit by Using Nano-Electronics Quantum Dot Cellular Method

Optimized buffer protection for network-on-chip based on Error Correction Code

Reliable NoC design with low latency and power consumption

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