NoC Dynamically Reconfigurable as TAM

Hybrid Test Data Transportation Scheme for Advanced NoC-Based SoCs

“…Unfortunately, they are not effective for NoC-based chips due to constraining the protocol and the topological position of cores. Keeping in view the future demand of on-chip network interconnect, several test schemes have been presented for NoC-based SoCs, which use NoC as TAM [1,3,[11][12][13][14][15][16][17][18][19]. All of these methods attempt to achieve test parallelism.…”

“…Moreover, it appends the constraint of topological positions of cores and access points (APs) into the test scheduling algorithms. Scheduling at high level of abstraction i.e., at packet or flit level, offers low controllability of test data paths [3]; however, the bus wires can be grouped and separately controlled. Therefore, test scheduling of NoC reuse results in relatively higher test time as compared to that of bus reuse, which is demonstrated by Fu et al [15] by comparing the test methods of conventional bus reuse as TAM [20][21][22][23][24] with that of NoC reuse [12,13,18,19].…”

“…Being motivated with the above review, both [15] and [3] presented test methods those embed DFT into the network routers to break the protocol constraint. With those configurations, the NoC communication hardware acts as traditional SoC TAM; however, the schedulers are constrained with the topological position of APs and CUTs.…”

“…• The proposed scheme for the test data transportation offers flexibility in selecting test scheduler without constraining the topological positions of APs and CUTs into the test scheduler, unlike [3,[15][16][17].…”

“…NoC has also been used as TAM to test the attached cores [1,3,[11][12][13][14][15][16][17][18][19]. In packet based NoC, communication is carried out via packets; therefore, in order to reuse it as a TAM, while complying with the network protocol, the test data needs to be transported in the form of packets.…”