2006
DOI: 10.1109/led.2006.882521
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NMOS Compatible Work Function of TaN Metal Gate With Gadolinium Oxide Buffer Layer on Hf-Based Dielectrics

Abstract: Reduction in effective work function (EWF) of midgap-tantalum nitride (TaN) metal gate with gadolinium-oxide buffer layer on Hafnium-based high-κ gate stack has been demonstrated. EWF of 4.2 eV is achieved for TaN with a bilayer arrangement of Gd 2 O 3 /HfSiO x dielectric. By using Gd-Si cosputtered layer on HfO 2 , a reduction in EWF to nMOS compatible value of 4.05 eV is obtained. Electrical and material characterization indicate that the conversion of gadolinium to gadolinium oxide and presence of silicon i… Show more

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Cited by 9 publications
(2 citation statements)
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References 14 publications
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“…Incorporating LaO into HfO 2 is reported to tune the TaN work function to 4.0 eV [5]. There are other two recent works which reported that Gd 2 O 3 and La 2 O 3 interfacial layers on the Hf-based oxide are able to tune the HfO 2 work function to 4.2 eV [14], [15]. In fact, the interfacial layer eventually mixes up with the underlying Hf-based oxide due to the diffusion during thermal process [15], resulting in a similar structure to this letter.…”
Section: Resultsmentioning
confidence: 99%
“…Incorporating LaO into HfO 2 is reported to tune the TaN work function to 4.0 eV [5]. There are other two recent works which reported that Gd 2 O 3 and La 2 O 3 interfacial layers on the Hf-based oxide are able to tune the HfO 2 work function to 4.2 eV [14], [15]. In fact, the interfacial layer eventually mixes up with the underlying Hf-based oxide due to the diffusion during thermal process [15], resulting in a similar structure to this letter.…”
Section: Resultsmentioning
confidence: 99%
“…[1][2][3] As the device miniaturizes, high-k dielectrics such as HfO 2 and metal gate electrodes such as titanium nitride (TiN), tantalum nitride (TaN) are used in production to boost device behaviors. [4][5][6] Various deposition conditions of the metal-gate layer can also induce a certain mount of mechanical stress which has not negligible effects on CMOS device performance. [7][8][9] The metal gate layer can be used as a new stressor for the channel.…”
Section: Introductionmentioning
confidence: 99%