The ever increasing requirements for electrical performance of on-chip wiring has driven three major technological advances in recent years. First, copper has replaced Aluminum as the new interconnect metal of choice, forcing also the introduction of damascene processing. Second, alternatives for SiO2 with a lower dielectric constant are being developed and introduced in main stream processing. The many new resulting materials needs to be classified in terms of their materials characteristics, evaluated in terms of their properties, and tested for process compatibility. Third, in an attempt to lower the dielectric constant even more, porosity is being introduced into these new materials. The study of processes such as plasma interactions and swelling in liquid media now becomes critical. Furthermore, pore sealing and the deposition of a thin continuous copper diffusion barrier on a porous dielectric are of prime importance. This review is an attempt to give an overview of the classification, the characteristics and properties of low-k dielectrics. In addition it addresses some of the needs for improved metrology for determining pore sizes, size distributions, structure, and mechanical properties.

This paper presents an in-depth overview of the present status and novel developments in the field of plasma processing of low dielectric constant (low-k) materials developed for advanced interconnects in ULSI technology. The paper summarizes the major achievements accomplished during the last 10 years. It includes analysis of advanced experimental techniques that have been used, which are most appropriate for low-k patterning and resist strip, selection of chemistries, patterning strategies, masking materials, analytical techniques, and challenges appearing during the integration. Detailed discussions are devoted to the etch mechanisms of low-k materials and their degradation during the plasma processing. The problem of k-value degradation (plasma damage) is a key issue for the integration, and it is becoming more difficult and challenging as the dielectric constant of low-k materials scales down. Results obtained with new experimental methods, like the small gap technique and multi-beams systems with separated sources of ions, vacuum ultraviolet light, and radicals, are discussed in detail. The methods allowing reduction of plasma damage and restoration of dielectric properties of damaged low-k materials are also discussed.

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The interaction between conventional and highly porous SiOCH with CF4, O2, and H2 plasma has been investigated. The highly porous SiOCH film has porosity about 40% and a k value about 2.2. The pristine SiOCH film has 19% of porosity and k value of 2.7. All experiments were performed at room temperature in a downstream plasma reactor. It was found that (i) the CF4 plasma etches the SiOCH film without bulk material modification (however, the etch rate was higher in the case of the SiOCH film with increased porosity); (ii) the O2 plasma oxidizes the SiOCH film converting the top layer to a hydrophilic SiO2-like porous material, the SiOCH film with increased porosity suffers more severely from this kind of plasma; (iii) the CF4/O2 plasma mixture has an optimal O2 concentration at which the etch rate is maximal; and (iv) the H2 plasma does not interact with the SiOCH film and can be a promising candidate for the resist stripping.

We report on a 65nm Ge pFET with a record performance of I on = 478µA/µm and I off,s = 37nA/µm @V dd = -1V. These improvements are quantified and understood with respect to halo/extension implants, minimizing series resistance and gate stack engineering. A better control of Ge in-diffusion using a low-temperature Epi-silicon passivation process allows achieving 1nm EOT Ge-pFET with increased performance. IntroductionRecently, 100nm Ge devices have shown similar intrinsic velocities and higher mobility compared to pMOS Si- (100) [1]. The high mobility/velocity at low V DS suggest Ge devices is an attractive option for future high performance MOS technologies. However, no results are available for GepMOSFET coupling low EOT and sub-70nm gate length. In this work, we demonstrate high performance p-channel Ge transistors with these two essential features.

We report a new curing procedure of a plasma enhanced chemical vapor deposited SiCOH glasses for interlayer dielectric applications in microelectronic. It is demonstrated that SiOCH glasses with improved mechanical properties and ultralow dielectric constant can be obtained by controlled decomposition of the porogen molecules used to create nanoscale pores, prior to the UV-hardening step. The Young's modulus ͑YM͒ of conventional SiOCH-based glasses with 32% open porosity hardened with porogen is 4.6 GPa, this value is shown to increase up to 5.2 GPa with even 46% open porosity, when the glasses are hardened after porogen removal. This increase in porosity is accompanied by significant reduction in the dielectric constant from 2.3 to 1.8. The increased YM is related to an enhanced molecular-bridging mechanism when film is hardened without porogen that was explained on the base of percolation of rigidity theory and random network concepts.

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When a Cu surface is exposed to a clean room ambient, a surface layer containing Cu 2 O, CuO, Cu͑OH͒ 2 , and CuCO 3 is formed. Thermal treatment in a vacuum combined with hydrogen plasma can remove this layer. Water and carbon dioxide desorb during the thermal treatment and the hydrogen plasma reduces the remaining Cu oxide. Ellipsometric, x-ray photoelectron spectroscopy, and time-of-flight secondary ion mass spectroscopy analyses indicate that the mechanism of interaction of the H 2 plasma with this layer depends on temperature. When the temperature is below 150°C, H 2 plasma cannot completely reduce Cu oxide. Hydrogen diffuses through the oxide and hydrogenation of the Cu layer is observed. The hydrogenated Cu surface has a higher resistance than a nontreated Cu layer. The hydrogen plasma efficiently cleans the Cu surface when the substrate temperature is higher than 150°C. In this case, hydrogen atoms have enough activation energy to reduce Cu oxide and adsorbed water forms as a byproduct of Cu oxide reduction. When the wafer temperature is higher than 350°C, the interaction of the Cu film with hydrogen and residual oxygen is observed.