Nine-state resonant tunneling diode memory

Seabaugh, Alan; Kao, Yung-Chung; Yuan, Huihua

doi:10.1109/55.192801

Cited by 108 publications

(33 citation statements)

References 18 publications

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“…In this case, the individual devices exhibit two NDR regions so that the latch has three stable voltage states. However, vertically integrated RTDs can be built with many current peaks and a RAM with up to nine states has been reported [43]. As the RTD is formed from a vertically layered stack, the logic devices may be simply built on top such that the top of the RTD mesa forms either the back gate of the DG CMOS device (Figure 9).…”

Section: Nano-scale Configuration Mechanismsmentioning

confidence: 99%

“…In the CNT case, a high resistance connection would to be made to bias the gate. Merging these technologies into an integrated unit will involve (amongst other challenges) matching the required configuration values (V G ) with the RTD tunneling voltages which are, in turn, determined by the thickness of each barrier layer in the RTDs [43]. While it has been suggested in [9] that III-V technology appears to be the most promising candidate for large scale integration of RTDs, silicon interband tunnel diodes with adequate room temperature peak-to-valley current ratios have recently been reported [19], [22] and may turn out to be easier and cheaper to fabricate.…”

Section: Nano-scale Configuration Mechanismsmentioning

confidence: 99%

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Exploiting multiple functionality for nano-scale reconfigurable systems

Beckett¹

2003

Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03

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It is likely that it will become increasingly difficult to manufacture the complex, heterogeneous logic structures that characterise current reconfigurable logic systems. As a result, these systems may come to be characterised by vast arrays of largely identical devices that are differentiated via postfabrication configuration -but only if low-overhead configuration can be achieved. Two simulation studies are presented that describe some ideas for achieving low-overhead reconfigurability in systems built from nano-scale components. The first is based on variable-threshold devices built from thin-body double gate transistors while a second, more speculative idea is based on recently identified resonant tunneling behaviour in carbon nanotubes. Various logic functions can be configured via the application of a simple bias voltage. Further, two approaches to the issue of generating the required bias voltages based on RTD devices and chalcogenide films are briefly explored.

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Section: Nano-scale Configuration Mechanismsmentioning

confidence: 99%

Section: Nano-scale Configuration Mechanismsmentioning

confidence: 99%

Exploiting multiple functionality for nano-scale reconfigurable systems

Beckett¹

2003

Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03

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“…In particular, the multiple-peak NDR circuits provide the convenience to implement the multiplevalued logic (MVL) circuit [3]- [5]. Compared to traditional binary logic, the MVL can transfer more information with fewer interconnects between devices and circuits.…”

Section: Introductionmentioning

confidence: 99%

Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources

Gan

Liang

Chen

2010

IEICE Trans. Inf. & Syst.

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SUMMARYThe paper demonstrates a novel multiple-valued logic (MVL) design using a three-peak negative differential resistance (NDR) circuit, which is made of several Si-based metal-oxide-semiconductor fieldeffect-transistor (MOS) and SiGe-based heterojunction bipolar transistor (HBT) devices. Specifically, this three-peak NDR circuit is biased by two switch-controlled current sources. Compared to the traditional MVL circuit made of resonant tunneling diode (RTD), this multiple-peak MOS-HBT-NDR circuit has two major advantages. One is that the fabrication of this circuit can be fully implemented by the standard BiCMOS process without the need for molecular-beam epitaxy system. Another is that we can obtain more logic states than the RTD-based MVL design. In measuring, we can obtain eight logic states at the output according to a sequent control of two current sources on and off in order.

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“…Functional density can be further improved by using vertically stacked RTDs in multistate memory and logic [12,13]. Analog circuits are also achievable, and a prototype 4 bit, 2 Gsps flash-ADC has been implemented [14].…”

Section: Introductionmentioning

confidence: 99%

Proposal to Develop Resonant-Tunneling Diode Circuits Using Epitaxial Liftoff

Brar¹,

Moise²

1999

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Nine-state resonant tunneling diode memory

Cited by 108 publications

References 18 publications

Exploiting multiple functionality for nano-scale reconfigurable systems

Exploiting multiple functionality for nano-scale reconfigurable systems

Novel Multiple-Valued Logic Design Using BiCMOS-Based Negative Differential Resistance Circuit Biased by Two Current Sources

Proposal to Develop Resonant-Tunneling Diode Circuits Using Epitaxial Liftoff

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