Next Generation High-Rate Telemetry

Ugolini, Alessandro; Montorsi, G.; Colavolpe, Giulio

doi:10.1109/jsac.2018.2804078

Cited by 5 publications

(2 citation statements)

References 30 publications

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“…Such coding and modulation schemes rely on Serially Concatenated Convolutional Codes (SCCCs), which are a class of Forward Error Correction (FEC) codes that are highly suitable for turbo (iterative) decoding. Currently, the CCSDS 131.2-B-1 constitutes a fundamental reference for telemetry (TM) downlink applications in Earth Exploration Satellite Services (EESSs) [2,3] such as geostationary Earth orbit (GEO)-to-ground and low Earth orbit (LEO)-to ground systems. In addition, in 2021, the CCSDS produced the 131.21-O-1 [4] standard, which tackles the increased throughput requirements of future missions through the utilization of advanced adaptive techniques.…”

Section: Introductionmentioning

confidence: 99%

Scalable Hardware-Efficient Architecture for Frame Synchronization in High-Data-Rate Satellite Receivers

Crocetti,

Pagani,

Bertolucci

et al. 2024

Electronics

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The continuous technical advancement of scientific space missions has resulted in a surge in the amount of data that is transferred to ground stations within short satellite visibility windows, which has consequently led to higher throughput requirements for the hardware involved. To aid synchronization algorithms, the communication standards commonly used in such applications define a physical layer frame structure that is composed of a preamble, segments of modulation symbols, and segments of pilot symbols. Therefore, the detection of a frame start becomes an essential operation, whose accuracy is undermined by the large Doppler shift and quantization errors in hardware implementations. In this work, we present a design methodology for frame synchronization modules that are robust against large frequency offsets and rely on a parallel architecture to support high throughput requirements. Several algorithms are evaluated in terms of the trade-off between accuracy and resource utilization, and the best solution is exemplified through its application to the CCSDS 131.2-B-1 and CCSDS 131.21-O-1 standards. The implementation results are reported for a Xilinx KU115 FPGA, thereby showing the capability of supporting baud rates that are greater than 2 Gbaud, as well as a corresponding throughput of 15.80 Gbps. To the best of our knowledge, this paper is the first to propose a design methodology for parallel frame synchronization modules that has applicability to the CCSDS 131.2-B-1 and CCSDS 131.21-O-1 standards.

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Section: Introductionmentioning

confidence: 99%

Scalable Hardware-Efficient Architecture for Frame Synchronization in High-Data-Rate Satellite Receivers

Crocetti,

Pagani,

Bertolucci

et al. 2024

Electronics

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“…Until today, CCSDS 131.2-B-1 has been regarded as a relatively new standard, generating little research attention. However, it is strongly endorsed by the European Space Agency (ESA) for next-generation applications in space communications [5].…”

Section: Introductionmentioning

confidence: 99%

CCSDS 131.2-B-1 Transmitter Design on FPGA with Adaptive Coding and Modulation Schemes for Satellite Communications

Coines

Jiménez

2021

Electronics

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Satellite communications are a well-established research area in which the main innovation of last decade has been the use of multi-carrier modulations and more robust channel coding techniques. However, in recent years, novel advanced signal processing has started being developed for these communications due to the increase in the signal processing capacity of transmitters and receivers. Although signal processing capabilities are increasing, they are still constrained by large limitations because these techniques need to be implemented in real hardware, thus making complexity a matter of critical importance. Therefore, this paper presents the design and implementation of a transmitter with adaptable coding and modulation on a field-programmable-gate-array (FPGA). The main motivation came from the standard CCSDS 131.2-B-1 which recommends that such a novel transmitter which has to date not been implemented in a real system The system was modeled by MATLAB with the purpose of being programmed in VHDL following the AXI-stream protocol between components. Behavioral simulation results were obtained in VIVADO and compared with MATLAB for verification purposes. The transmitter logical circuit was synthesized in a FPGA Zynq Ultrascale RFSoC ZU28DR, showing low resource consumption and correct functioning, leading us to conclude that the deployment of new communication systems in state-of-the-art hardware in satellite communications is justified.

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FPGA Based Transmitter Design Using Adaptive Coding and Modulation Schemes for Low Earth Orbit Satellite Communications

Inceoz

Tutgun

Turgut

2020

2020 IEEE 5th International Symposium on Telecommunication Technologies (ISTT)

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Next Generation High-Rate Telemetry

Cited by 5 publications

References 30 publications

Scalable Hardware-Efficient Architecture for Frame Synchronization in High-Data-Rate Satellite Receivers

Scalable Hardware-Efficient Architecture for Frame Synchronization in High-Data-Rate Satellite Receivers

CCSDS 131.2-B-1 Transmitter Design on FPGA with Adaptive Coding and Modulation Schemes for Satellite Communications

FPGA Based Transmitter Design Using Adaptive Coding and Modulation Schemes for Low Earth Orbit Satellite Communications

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