CCSDS 131.2-B-1 Transmitter Design on FPGA with Adaptive Coding and Modulation Schemes for Satellite Communications

Coines, Adrián Lamoral; Jiménez, Víctor P. Gil

doi:10.3390/electronics10202476

Cited by 5 publications

(3 citation statements)

References 8 publications

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“…The characteristics of the proposed SoftMax implementation were evaluated through simulations on Field-Programmable Gate Arrays (FPGA). FPGAs are widely used in the research and development of state-of-the-art computing systems, and numerous useful software tools are available [6,7,23].…”

Section: Resultsmentioning

confidence: 99%

“…Hardware accelerators are well optimized specifically for machine-learning algorithms, performance, and power efficiency. The significance of hardware accelerators is particularly pronounced in mobile and standalone systems, such as mobile robots, smartphones, unmanned aerial vehicles (UAVs), self-driving cars, satellites, smart Internet of Things (IoT) sensors, edge computing nodes, and various other devices [1][2][3][4][5][6][7][8]. These systems impose stringent requirements on factors such as durability, weight, and battery life.…”

Section: Introductionmentioning

confidence: 99%

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Implementation of the SoftMax Activation for Reconfigurable Neural Network Hardware Accelerators

Shatravin,

Shashev,

Shidlovskiy

2023

Applied Sciences

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In recent decades, machine-learning algorithms have been extensively utilized to tackle various complex tasks. To achieve the high performance and efficiency of these algorithms, various hardware accelerators are used. Typically, these devices are specialized for specific neural network architectures and activation functions. However, state-of-the-art complex autonomous and mobile systems may require different algorithms for different tasks. Reconfigurable accelerators can be used to resolve this problem. They possess the capability to support diverse neural network architectures and allow for significant alterations to the implemented model at runtime. Thus, a single device can be used to address entirely different tasks. Our research focuses on dynamically reconfigurable accelerators based on reconfigurable computing environments (RCE). To implement the required neural networks on such devices, their algorithms need to be adapted to the homogeneous structure of RCE. This article proposes the first implementation of the widely used SoftMax activation for hardware accelerators based on RCE. The implementation leverages spatial distribution and incorporates several optimizations to enhance its performance. The timing simulation of the proposed implementation on FPGA shows a high throughput of 1.12 Gbps at 23 MHz. The result is comparable to counterparts lacking reconfiguration capability. However, this flexibility comes at the expense of the increased consumption of logic elements.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Implementation of the SoftMax Activation for Reconfigurable Neural Network Hardware Accelerators

Shatravin,

Shashev,

Shidlovskiy

2023

Applied Sciences

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“…Such coding and modulation schemes rely on Serially Concatenated Convolutional Codes (SCCCs), which are a class of Forward Error Correction (FEC) codes that are highly suitable for turbo (iterative) decoding. Currently, the CCSDS 131.2-B-1 constitutes a fundamental reference for telemetry (TM) downlink applications in Earth Exploration Satellite Services (EESSs) [2,3] such as geostationary Earth orbit (GEO)-to-ground and low Earth orbit (LEO)-to ground systems. In addition, in 2021, the CCSDS produced the 131.21-O-1 [4] standard, which tackles the increased throughput requirements of future missions through the utilization of advanced adaptive techniques.…”

Section: Introductionmentioning

confidence: 99%

Scalable Hardware-Efficient Architecture for Frame Synchronization in High-Data-Rate Satellite Receivers

Crocetti,

Pagani,

Bertolucci

et al. 2024

Electronics

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The continuous technical advancement of scientific space missions has resulted in a surge in the amount of data that is transferred to ground stations within short satellite visibility windows, which has consequently led to higher throughput requirements for the hardware involved. To aid synchronization algorithms, the communication standards commonly used in such applications define a physical layer frame structure that is composed of a preamble, segments of modulation symbols, and segments of pilot symbols. Therefore, the detection of a frame start becomes an essential operation, whose accuracy is undermined by the large Doppler shift and quantization errors in hardware implementations. In this work, we present a design methodology for frame synchronization modules that are robust against large frequency offsets and rely on a parallel architecture to support high throughput requirements. Several algorithms are evaluated in terms of the trade-off between accuracy and resource utilization, and the best solution is exemplified through its application to the CCSDS 131.2-B-1 and CCSDS 131.21-O-1 standards. The implementation results are reported for a Xilinx KU115 FPGA, thereby showing the capability of supporting baud rates that are greater than 2 Gbaud, as well as a corresponding throughput of 15.80 Gbps. To the best of our knowledge, this paper is the first to propose a design methodology for parallel frame synchronization modules that has applicability to the CCSDS 131.2-B-1 and CCSDS 131.21-O-1 standards.

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CCSDS 131.2-B-1 Serial Concatenated Convolutional Turbo Decoder Architecture for Efficient FPGA Implementation

Naranjo

Jiménez

2023

IEEE Access

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Most of the turbo encoding schemes at standards are parallel-based, so different architectures for efficient implementation are common in the literature. However, a serial turbo decoder is not that common. This scheme is used in CCSDS 131.2-B-1 standard, which is attracting much of attention recently due to its higher performance for satellite communications. In this paper, an efficient architecture for the decoder is proposed and analyzed. It is intended to show an architecture that can be modeled in a circuit description language (such as VHDL and Verilog) in such a way that it can be easily implemented on a Field Programmable Gate Array (FPGA). This work describes in detail this architecture explaining the encoding operations that are performed at the transmitter and then, how to undo them at the receiver. The proposed algorithm works by using independent components to divide the tasks and to obtain a pipeline architecture to improve the efficiency. The results of simulating and implementing the proposed architecture on a Xilinx Zynq UltraScale+ RFSoC ZCU28DR board with XCZU28DR-2FFVG1517E RFSoC are shown. The final results presented demonstrate how the hardware operations give equivalent results to the software simulation and do not consume board resources aggressively as usually the turbodecoder does.

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CCSDS 131.2-B-1 Transmitter Design on FPGA with Adaptive Coding and Modulation Schemes for Satellite Communications

Cited by 5 publications

References 8 publications

Implementation of the SoftMax Activation for Reconfigurable Neural Network Hardware Accelerators

Implementation of the SoftMax Activation for Reconfigurable Neural Network Hardware Accelerators

Scalable Hardware-Efficient Architecture for Frame Synchronization in High-Data-Rate Satellite Receivers

CCSDS 131.2-B-1 Serial Concatenated Convolutional Turbo Decoder Architecture for Efficient FPGA Implementation

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