New understanding of LDD CMOS hot-carrier degradation and device lifetime at cryogenic temperatures

Wang-Ratkovic, J.; Lacoe, R.C.; MacWilliams, K.P.; Song, Miryeong; Brown, Stephanie; Yabiku, G.K.

doi:10.1109/relphy.1997.584280

Cited by 38 publications

(16 citation statements)

References 8 publications

(4 reference statements)

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“…We present NMOS HC lifetime data over the stress drain voltage range V 2.9 V and the full range from below to above that show disagreement with the LEM. Moreover, these data are consistent with our proposed effective electron temperatures [9], [10] that for HC degradation in short NMOS devices, the worst case is not near the peak substrate current point (as predicted by the LEM), but at high .…”

Section: Introductionsupporting

confidence: 89%

Impact of E-E scattering to the hot carrier degradation of deep submicron NMOSFETs

Rauch

Guarin

LaRosa

1998

IEEE Electron Device Lett.

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The hot carrier degradation of short channel NMOS-FET's (L L L EFF = = = 0.07-0.10 m) stressed at 2.0 V V DS V DS V DS 2.9 V and a wide V GS V GS V GS range is shown NOT to obey the classic hot carrier "lucky electron model." In the low and mid V GS V GS V GS range, the degradation behavior is better described by an effective electron temperatures model proposed here, which takes e-e scattering effects into account. In the high V GS V GS V GS regime, a further lifetime reduction can be qualitatively explained within this model by the increase in electron concentration at the Si-SiO 2 interface near the drain region.Index Terms-Accelerated stress, e-e scattering, effective electron temperatures, hot carrier degradation, interface state generation, lifetime projection, lucky electron model, reliability.

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Section: Introductionsupporting

confidence: 89%

Impact of E-E scattering to the hot carrier degradation of deep submicron NMOSFETs

Rauch

Guarin

LaRosa

1998

IEEE Electron Device Lett.

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“…Room temperature measurements also showed a clear lifetime dependence on width. This observation is new and is even contrary to statements made in previous publications [1] [10]. The smaller transistors were subject to a larger degree of degradation having verifiably shorter lifetimes.…”

Section: Results From 064µm/013µmcontrasting

confidence: 87%

“…ryogenic operation improves all aspects of device performance such as speed, noise, and current drive [1]. However, these performance improvements may come at a cost of reduced device and circuit reliability.…”

Section: Introductionmentioning

confidence: 99%

“…The reason for the increase is straightforward: at low temperatures, phonon scattering is reduced and therefore the carrier mean-free path length is increased. Thus, the damage can occur much faster at cryogenic temperatures than at room temperature for a fixed stress condition [1] [2]. With the increased mean-free path length, the probability that a carrier will obtain enough energy to cause impact ionization also increases.…”

Section: Introductionmentioning

confidence: 99%

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Lifetime Studies of 130 nm nMOS Transistors Intended for Long-Duration, Cryogenic High-Energy Physics Experiments

Hoff

Arora

Cressler

et al. 2012

IEEE Trans. Nucl. Sci.

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Abstract-Future neutrino physics experiments intend to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. To increase performance, integrated readout electronics should work inside the cryostat. Due to the scale and cost associated with evacuating and filling the cryostat, the electronics will be unserviceable for the duration of the experiment. Therefore, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is via hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130nm nMOS transistors operating at cryogenic temperatures are investigated. The results show that the difference in lifetime for room temperature operation and cryogenic operation for this process are not great and the lifetimes at both 300K and at 77K can be projected to more than 20 years at the nominal voltage (1.5V) for this technology.

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“…At temperature lower than -55°C, hot carrier aging becomes a reliability concern [4][5][6][7][8][9]. Hot carrier aging tests were performed on the 0.35gm SOI transistors at room temperature, -120°C and -160°C.…”

Section: Designfor Op-amp Reliabilitymentioning

confidence: 99%

Design and Qualification Methodology for a Successful Technology Infusion for a Wide Temperature Op-Amp

Yuan

Mojaradi

Aranki

et al. 2008

2008 IEEE Aerospace Conference

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In this paper' , we present a methodology for design and qualification of microelectronics for low temperature applications, which has enabled the successful infusion of a custom designed Operational Amplifier into flight mission. The Op-Amp was designed to target a wide temperature range of -150°C to +125°C for at least 5 years operation for Mars Mission. The design and qualification methodology developed have provided the critical path for the technology infusion.

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New understanding of LDD CMOS hot-carrier degradation and device lifetime at cryogenic temperatures

Cited by 38 publications

References 8 publications

Impact of E-E scattering to the hot carrier degradation of deep submicron NMOSFETs

Impact of E-E scattering to the hot carrier degradation of deep submicron NMOSFETs

Lifetime Studies of 130 nm nMOS Transistors Intended for Long-Duration, Cryogenic High-Energy Physics Experiments

Design and Qualification Methodology for a Successful Technology Infusion for a Wide Temperature Op-Amp

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