Lifetime Studies of 130 nm nMOS Transistors Intended for Long-Duration, Cryogenic High-Energy Physics Experiments

Abstract

Abstract-Future neutrino physics experiments intend to use unprecedented volumes of liquid argon to fill a time projection chamber in an underground facility. To increase performance, integrated readout electronics should work inside the cryostat. Due to the scale and cost associated with evacuating and filling the cryostat, the electronics will be unserviceable for the duration of the experiment. Therefore, the lifetimes of these circuits must be well in excess of 20 years. The principle mechanism for lifetime degradation of MOSFET devices and circuits operating at cryogenic temperatures is via hot carrier degradation. Choosing a process technology that is, as much as possible, immune to such degradation and developing design techniques to avoid exposure to such damage are the goals. This requires careful investigation and a basic understanding of the mechanisms that underlie hot carrier degradation and the secondary effects they cause in circuits. In this work, commercially available 130nm nMOS transistors operating at cryogenic temperatures are investigated. The results show that the difference in lifetime for room temperature operation and cryogenic operation for this process are not great and the lifetimes at both 300K and at 77K can be projected to more than 20 years at the nominal voltage (1.5V) for this technology.

Cryogenic Lifetime Studies of 130 nm and 65 nm nMOS Transistors for High-Energy Physics Experiments

“…In previous lifetime tests [8], [9], a simple liquid nitrogen bath was used to keep the stressed devices at cryogenic temperatures. This technique, while simple and effective, has practical limitations.…”

“…More recent studies, however, suggest that the evolution of CMOS technology and, in particular, the continued reduction in operating voltage is minimizing the significance of operating temperature on device lifetimes [8]- [11]. This paper is a continuation of that research [8] in a CMOS 130 nm technology. More importantly, since the stated intention of the High Energy Physics VLSI community is to work in 65 nm in the foreseeable future [12]- [14], lifetime studies are extended to this node as well.…”

“…Unfortunately, early research declared that cryogenic operation may dramatically reduce device and circuit lifetimes [6], [7]. More recent studies, however, suggest that the evolution of CMOS technology and, in particular, the continued reduction in operating voltage is minimizing the significance of operating temperature on device lifetimes [8]- [11]. This paper is a continuation of that research [8] in a CMOS 130 nm technology.…”

“…Hot-carrier degradation has traditionally been evaluated under as the worst-case stress condition [8], [21], [22]. However, dependences of the worst-case stress condition on channel length, drain bias and temperature have been observed [3], [23].…”

A Simulation Study of Hot Carrier Effects in SoI-Like Bulk Silicon nMOS Device

“…HCE of MOSFET has been studied by a lot of scholars and great progress has been made [2]- [4]. Many attempts have been made to improve the HCE of MOS devices.…”