Cryogenic Lifetime Studies of 130 nm and 65 nm nMOS Transistors for High-Energy Physics Experiments

Hoff, J.; Deptuch, G.; Wu, Guoying; Gui, Ping

doi:10.1109/tns.2015.2433793

Cited by 36 publications

(12 citation statements)

References 18 publications

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“…Therefore, good long-term reliability under temperature stress is critical to the success of ColdADC_P2. The DUNE Collaboration undertook extensive empirical studies of cold-temperature reliability of devices implemented in 65 nm CMOS technology [7]. These studies resulted in a set of design guidelines that were followed in the design of ColdADC_P2 to ensure long-term reliability.…”

Section: Coldadc_p2mentioning

confidence: 99%

See 1 more Smart Citation

ColdADC_P2: A 16-Channel Cryogenic ADC ASIC for the Deep Underground Neutrino Experiment

Grace

Braga

Chen

et al. 2022

IEEE Trans. Nucl. Sci.

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The second and final version of ColdADC, called ColdADC_P2, is presented. ColdADC_P2 is a 16-channel, 12-bit, 2 MS/s Digitizer ASIC intended for use inside the DUNE Far Detector. ColdADC_P2 contains two 16 MS/s Pipelined ADCs that each digitizes the output of 8 sample-and-hold amplifiers. Because the application requires immersion in liquid argon, ColdADC_P2 was developed using specialized design techniques for long-term reliability in cryogenic environments and a customized cryogenic standard cell library. ColdADC_P2, with a die area of approximately 52.4 mm 2 and fabricated in 65 nm CMOS technology, achieves 130 µV-rms noise performance and 11.8-bit ENOB at a temperature of 77 K, with channel-to-channel crosstalk of < 0.06% while dissipating 338 mW (21 mW per channel). Residual nonlinearity that is consistent with dielectric absorption in the capacitors internal to the ADC is corrected using a lookup table.

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Section: Coldadc_p2mentioning

confidence: 99%

“…In addition, a custom digital standard cell library was developed that embodies these design guidelines [3]. Custom cryogenic simulation models based on measured test structures were also used to ensure that the analog circuits in ColdADC_P2 were appropriately simulated [7].…”

Section: Coldadc_p2mentioning

confidence: 99%

ColdADC_P2: A 16-Channel Cryogenic ADC ASIC for the Deep Underground Neutrino Experiment

Grace

Braga

Chen

et al. 2022

IEEE Trans. Nucl. Sci.

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“…The low-temperature circuits developed for spacecraft [19], [20], scientific equipment [21], ultralow-noise detectors [22], cryobiology [23], and others have been custom-designed relying on a semiempirical approach. This approach requires laborious and expensive low-temperature measurements to extract model parameters for tuning RT compact models to the target low temperature [22], [24], [25].…”

Section: Cryo-mos Transistor Modelingmentioning

confidence: 99%

Cryogenic MOS Transistor Model

Beckers

Jazaeri

Enz

2018

IEEE Trans. Electron Devices

138

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This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is developed relying on the 1-D Poisson equation and the drift-diffusion transport mechanism. The validity of the Maxwell-Boltzmann approximation is demonstrated in the limit to 0 K as a result of dopant freezeout in cryogenic equilibrium. Explicit MOS transistor expressions are then derived, including incomplete dopant ionization, bandgap widening, mobility reduction, and interface charge traps. The temperature dependence of the interface trapping process explains the discrepancy between the measured value of the subthreshold swing and the thermal limit at deep-cryogenic temperatures. The accuracy of the developed model is validated by experimental results on long devices of a commercial 28-nm bulk CMOS process. The proposed model provides the core expressions for the development of physically accurate compact models dedicated to low-temperature CMOS circuit simulation. Index Terms-Cryo-CMOS, cryogenic MOSFET, freezeout, incomplete ionization, interface traps, low temperature, MOS transistor, physical modeling. I. INTRODUCTION A DVANCED CMOS processes perform increasingly well from room temperature (RT) down to deep-cryogenic temperatures (<10 K) [1]-[3]. At these temperatures, the ideal switch with a steplike subthreshold slope comes within reach [4]. Furthermore, cryoelectronics [5]-[7] can provide an interface with superconducting devices on the quest for exascale supercomputing [8]. Ultimately, quantum-engineered devices controlled by cryo-CMOS circuits can bring new functionality to existing computing technologies [9], [10]. Large-scale integration of silicon spin qubits [11], [12] and cryo-CMOS control circuits is envisioned to take solid-state quantum computing to the next level [13]. Digital, analog, and RF CMOS circuits [14]-[16] are then required to operate at millikelvin temperatures for initialization, manipulation, and readout of the qubits, as well as error correction [17], [18].

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“…Studies conducted at BNL indicate charge carrier mobility in silicon increases and thermal fluctuations decrease with kT/e at 77 K -89 K, resulting in a higher gain, higher g m /I D , higher speed and lower noise. Channel Hot Carry Effect (HCE), which is the only remaining aging mechanism that affects the lifetime of CMOS devices at cryogenic temperature, is evaluated as well [5,6,7]. A 16-channel FE ASIC which is suitable for 77 K -300 K operation with long lifetime and low power consumption is designed.…”

Section: Cold Electronicsmentioning

confidence: 99%

Low Noise Cold Electronics System for SBND LAr TPC

Gao¹

2019

Preprint

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The Short Baseline Near Detector (SBND) is one of three liquid argon (LAr) neutrino detectors sitting in the Booster Neutrino Beam (BNB) at Fermilab as part of the Short Baseline Neutrino (SBN) program. The detector is in a cryostat holding 260-ton of LAr and consists of four 2.5 m (L) × 4 m (W) Anode Plane Assembles (APAs) and two Cathode Plane Assemblies (CPAs), which leads to 11,264 Time Projection Chamber (TPC) readout channels and two separate 2 m long drift regions. As an enabling technology, Cold Electronics (CE) developed for cryogenic temperature operation makes possible an optimum balance among various design and performance requirements for such large sized detectors. Brookhaven National Laboratory (BNL) has been leading the R&D and implementation of the entire front-end CE system for LAr TPC readout in collaboration with other SBND institutes. The front-end readout electronics system includes the cold front-end electronics placed close to the wire electrodes, which detects and digitizes the charge signal in LAr, as well as the warm interface electronics placed on the signal feed-through flange outside of the cryostat, which further organizes and transmits the digitized signal to the DAQ system. An extensive study of electronics suitable for 77 K -300 K, including the custom designed front-end ASIC and commercial components, e.g. ADC and FPGA, has been made to meet requirements such as low noise, low power consumption, high reliability and long lifetime. Furthermore, an integral design concept of APA, CE, feed-through, warm interface electronics with local diagnostics, grounding and isolation rules has been practiced with vertical slice test stands to make projection of the CE performance in the SBND detector.

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Cryogenic Lifetime Studies of 130 nm and 65 nm nMOS Transistors for High-Energy Physics Experiments

Cited by 36 publications

References 18 publications

ColdADC_P2: A 16-Channel Cryogenic ADC ASIC for the Deep Underground Neutrino Experiment

ColdADC_P2: A 16-Channel Cryogenic ADC ASIC for the Deep Underground Neutrino Experiment

Cryogenic MOS Transistor Model

Low Noise Cold Electronics System for SBND LAr TPC

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