New test data decompressor for low power applications

Mrugalski, Grzegorz; Rajski, J.; Czysz, D.; Tyszer, Jerzy

doi:10.1145/1278480.1278617

Cited by 36 publications

(26 citation statements)

References 34 publications

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“…Methods are proposed to utilize the don't-care bits to minimize the scanin transitions for a given test set [Mrugalski et al 2007;Li et al 2008;Lin et al 2006;Sankaralingam et al 2000;Sinanoglu et al 2003]. Sankaralingam et al [2000] proposed a don't-care-filling technique, named MT-fill, guaranteeing that the scan-in transitions generated by its filled patterns are minimum for the given test set and scan-cell ordering.…”

Section: Introductionmentioning

confidence: 99%

“…Sankaralingam et al [2000] proposed a don't-care-filling technique, named MT-fill, guaranteeing that the scan-in transitions generated by its filled patterns are minimum for the given test set and scan-cell ordering. The methods in Sankaralingam et al [2000], Mrugalski et al [2007], Lin et al [2006] reduced the test power as well as the test data volume based on built-in decompression hardware. Sinanoglu et al [2003] added Xor gates or inverters along the scan paths to minimize the scan-in transitions.…”

Section: Introductionmentioning

confidence: 99%

“…However, one serious disadvantage in the scan-chain-reordering techniques [Bonhomme et al 2002[Bonhomme et al , 2003[Bonhomme et al , 2004Dabholkar et al 1998] is that the exact test patterns and responses need to be obtained in advance. As the result, no don't-care bits can be utilized for a further reduction to scan-in transitions or test data volume, such as Sankaralingam et al [2000], Mrugalski et al [2007], Lin et al [2006], Sinanoglu et al [2003], Li et al [2008]. Sinanoglu et al [1998] can reorder the scan cells based on the test set with don't-care bits.…”

Section: Introductionmentioning

confidence: 99%

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Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes

Chao

2010

ACM Trans. Des. Autom. Electron. Syst.

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This article presents several scan-cell reordering techniques to reduce the signal transitions during the test mode while preserving the don't-care bits in the test patterns for a later optimization. Combined with a pattern-filling technique, the proposed scan-cell reordering techniques can utilize both high response correlations and pattern correlations to simultaneously minimize scan-out and scan-in transitions. Those scan-shift transitions can be further reduced by selectively using the inverse connections between scan cells. In addition, the trade-off between routing overhead and power consumption can also be controlled by the proposed scan-cell reordering techniques. A series of experiments are conducted to demonstrate the effectiveness of each of the proposed techniques individually.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes

Chao

2010

ACM Trans. Des. Autom. Electron. Syst.

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“…A common technique is to repeat the value of the most recent care-bit [11,12]. The same effect can be achieved by adding a mask register [13,14] or by using a shadow register [15]. The clustering of the scan-cells into chains has significant impact on the aforementioned techniques.…”

Section: Introductionmentioning

confidence: 99%

“…Hence, scan chain clustering does not introduce any additional impact in the tool flow. The clustering is independent of the test set and may be combined with any of the power optimization techniques in [8,9,10,11,12,13,14,15]. In the sequel, the BIST-based power optimization method from [10] is used to evaluate the synthesized scan configurations for benchmark circuits and large industrial circuits.…”

Section: Introductionmentioning

confidence: 99%

Scan chain clustering for test power reduction

Elm

Wunderlich

Imhof

et al. 2008

Proceedings of the 45th Annual Design Automation Conference

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An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-flops into scan chains, which determines how many chains can be deactivated per pattern. In this paper, a new method to cluster flip-flops into scan chains is presented, which minimizes the power consumption during test. It is not dependent on a test set and can improve the performance of any test power reduction technique consequently. The approach does not specify any ordering inside the chains and fits seamlessly to any standard tool for scan chain integration. The application of known test power reduction techniques to the optimized scan chain configurations shows significant improvements for large industrial circuits.

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Test Power Reduction by Blocking Scan Cell Outputs

Lin

Rajski

2008

2008 17th Asian Test Symposium

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New test data decompressor for low power applications

Cited by 36 publications

References 34 publications

Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes

Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified Test Cubes

Scan chain clustering for test power reduction

Test Power Reduction by Blocking Scan Cell Outputs

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