New MTCMOS Flip-Flops with Simple Control Circuitry and Low Leakage Data Retention Capability

Liu, Zhiyu; Kursun, Volkan

doi:10.1109/icecs.2007.4511230

Cited by 17 publications

(16 citation statements)

References 6 publications

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“…Second, SRFFs have a higher dynamic power consumption than their conventional counterparts: In [15] an active power overhead of 26% is reported for Ballon SRFF compared to standard FF. [10] reports an overhead of 46-49% for the Ballon SRFF, which matches with our own analog simulations of SRFF standard cells in 40nm of 27% and 42% for a live-latch and balloon SRFF respectively. By reusing the scan chains to implement an out-of-place state saving, as we propose, the conventional scan-flip-flops are not replaced and thus an increase in active power is avoided.…”

Section: Related Worksupporting

confidence: 66%

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A scan-chain based state retention methodology for IoT processors operating on intermittent energy

Hager

Fatemi

Gyvez

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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Abstract-Future IoT systems are tightly constraint by cost and size and will often be operated from an energy harvester's output. Since these batteryless systems operate on intermittent energy they have to be able to retain their state during the power outages in order to guarantee computation progress. Due to the lack of large energy buffers the state needs to be saved quickly using residual energy only. In related work, the state is retained in-place by replacing all flip-flops with state retentive flip-flops (SRFF), which are powered by auxiliary supplies for retention or incorporate non-volatile memory cells. However, these SRFFs increase the power consumption during active operation impairing the overall systems efficiency. In this paper, we present a scan-chain based state retention approach, where the state is moved to memory using only 4.5pJ/b. Since our approach does not introduce any power overhead, this energy cost pays off after an on-time of just 100us compared to state-of-the-art inplace solutions. Moreover, compared to a software mechanism, our approach requires 6.6x less energy to move the state and is 5.8x faster.

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Section: Related Worksupporting

confidence: 66%

“…Life-latch based SRFF retain the state in the slave latch by not power gating the slave latch and the clock signal. Both are volatile and require virtually no energy to switch to retention mode, but around 0.1-1nW/b [10] must be supplied to retain the state.…”

Section: Related Workmentioning

confidence: 99%

A scan-chain based state retention methodology for IoT processors operating on intermittent energy

Hager

Fatemi

Gyvez

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

View full text Add to dashboard Cite

show abstract

“…Among the extra circuitry to implement power-gating, data-retention flip-flop represents the biggest overhead. A data-retention flip-flop [3], [5], [8]- [10] preserves a data in an extra latch, which is fully biased during standby mode since it is never power-gated. Therefore, all the extra latches induce continuous gate leakage, take extra area, and are wired to power-management unit (PMU).…”

Section: Introductionmentioning

confidence: 99%

Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS

Kim

Lee

Kim

et al. 2010

IEEE Trans. VLSI Syst.

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Power-gating has been widely used to reduce subthreshold leakage current. However, the extent of leakage saving through power-gating diminishes with technology scaling due to gate leakage of data-retention circuit elements. Furthermore, power-gating involves substantial increase of area and wirelength. A circuit technique called supply switching with ground collapse (SSGC) has recently been proposed to overcome the limitation of power-gating. The circuit technique is successfully applied to the register file of ARM9 microprocessor in a 1.2 V, 65-nm CMOS process, and the measured result is reported for the first time. The leakage current is reduced by a factor of 960 on average of 83 dies at 25 C, and by a factor of 150 at 85 C. Compared to a register file implemented in conventional power-gating, leakage current is cut by a factor of 2.2, demonstrating that SSGC can be a substitute for power-gating in nanometer CMOS.

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“…Power gating technique is an effective method to reduce the leakage in sequential circuits during standby mode [2,5,13,15,16]. Retaining the circuit state during the sleep mode is highly significant in power gating sequential circuits.…”

Section: Previous Work Reviewmentioning

confidence: 99%

“…Data retention function is essential for sequential circuits which need to restore the data after they are woken up and make sure that the correct data can be transferred to the output [5,13].…”

Section: Introductionmentioning

confidence: 99%

A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

Fan

Dong

et al. 2014

Journal of Electrical and Computer Engineering

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With the scaling of technology process, leakage power becomes an increasing portion of total power. Power gating technology is an effective method to suppress the leakage power in VLSI design. When the power gating technique is applied in sequential circuits, such as flip-flops and latches, the data retention is necessary to store the circuit states. A low leakage autonomous data retention flip-flop (ADR-FF) is proposed in this paper.

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New MTCMOS Flip-Flops with Simple Control Circuitry and Low Leakage Data Retention Capability

Cited by 17 publications

References 6 publications

A scan-chain based state retention methodology for IoT processors operating on intermittent energy

A scan-chain based state retention methodology for IoT processors operating on intermittent energy

Supply Switching With Ground Collapse for Low-Leakage Register Files in 65-nm CMOS

A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

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