A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

Abstract

With the scaling of technology process, leakage power becomes an increasing portion of total power. Power gating technology is an effective method to suppress the leakage power in VLSI design. When the power gating technique is applied in sequential circuits, such as flip-flops and latches, the data retention is necessary to store the circuit states. A low leakage autonomous data retention flip-flop (ADR-FF) is proposed in this paper.

Performance Evaluation of Master–Slave D Flip Flop Based on Charge Retention Feedback Pass Transistor Logic in Nanotechnology

“…A complex charge retention circuit is needed to retain the charge stored in the circuit when transition takes place from active to sleep and sleep to active mode. Autonomous Data Retention Flip Flop [17] is used to reduce power consumption when the circuit is in sleep and idle mode for long time, but the disadvantage is that it increases the size of circuit due to increased size of high threshold sleep transistors. More power consumption takes place when the circuit transitions from active to sleep mode and vice versa.…”

A 380 fW Leakage Data Retention Flip-Flop for Short Sleep Periods

“…In the prior art there are two approaches to achieve a low leakage flip-flop (FF) with data retention capability 1) nonvolatile data retention FF (NV-FF) [1], [2], [3], [4], [5], [6], [7], [8], [9], [10] and 2) CMOS FF with a balloon latch (DR-FF). The NV-FF allows zero power consumption to maintain the data during the sleep mode, whereas the DR-FF requires an always-on circuity to preserve the data [11], [12], [13], [14], [15], [16]. Nevertheless, NV-FFs have several disadvantages over CMOS DR-FFs, particularly for duty-cycled systems with short and frequent sleep modes.…”