New low-power techniques: Leakage Feedback with Stack &amp;amp; Sleep Stack with Keeper

Pal, Pankaj Kumar; Rathore, Rituraj Singh; Rana, Ashwani K.; Saini, Gaurav

doi:10.1109/iccct.2010.5640514

Cited by 21 publications

(3 citation statements)

References 7 publications

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“…This is shown in figure 2. In order for the logic circuits to maintain high switching speeds, they use low threshold voltage transistors [9][10][11]. The leakage power is reduced in the sleep transistor using sleep mode by isolating them with the logic circuits.…”

Section: Sleep Transistormentioning

confidence: 99%

Implementation and modeling of low power sleepy stack SRAM cell

Kakkar¹,

Goyal²,

Singh³

et al. 2019

CGCIJCTR

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for the future technologies in which the devices and circuits are integrating more, low power consuming devices are needed. Mostly the reduction of power dissipation work is concentrated on switching and leakage current. However sub threshold current is also a big factor which leads to power consumption especially for memories. In this paper, leakage power of SRAM memory cell is reduced by power gated sleepy stack structure which leads to lesser power dissipation. The power dissipation is reduced to 226 µW with proposed technique compared with power dissipation of conventional 6T SRAM cell which had 740 µW. With lesser power dissipation the circuit can have more battery backup and lesser heat emission

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Section: Sleep Transistormentioning

confidence: 99%

Implementation and modeling of low power sleepy stack SRAM cell

Kakkar¹,

Goyal²,

Singh³

et al. 2019

CGCIJCTR

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show abstract

“…However for shrink in feature size to 0.09 micrometre (0.09 µm) to 0.065 micro meter (0.065 µm) static power dissipation became a challenge for today's and in future technologies. Increase in subthreshold leakage power increasers dynamic power dissipation and as threshold power decreases due to scaling of circuit sub-threshold leakage power increases exponentially [9][10][11][12][13]. The sub threshold leakage current in nMOS is shown in figure 1.…”

Section: Introductionmentioning

confidence: 99%

Implementation and Modeling of Low Power Sleepy Stack Sram

Kakkar¹

2022

joas

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For the future technologies in which the devices and circuits are integrating more, low power consuming devices are needed. Mostly the reduction of power dissipation work is concentrated on switching and leakage current. However, sub threshold current is also a big factor which leads to power consumption especially for memories. In this paper, leakage power of SRAM memory cell is reduced by power gated sleepy stack structure which leads to lesser power dissipation. The power dissipation is reduced to 226 µW with proposed technique compared with power dissipation of conventional 6T SRAM cell which had 740 µW. With lesser power dissipation the circuit can have more battery backup and lesser heat emission

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“…The low power architecture of SRAM (Static Random-Access Memory) plays a dominant role in various applications due to its speed and long-term resistance [3]. Configurable Logic Block (CLB) is a major block in VLSI design involved devices like SPARTAN and VIRTEX architecture [4][5]15]. CLB consist of 20% to 30% SRAM cell [16] because it has the advantage of reprogrammable capability and speed.…”

Section: Introductionmentioning

confidence: 99%

KLECTOR: Design of Low Power Static Random-Access Memory Architecture with reduced Leakage Current

Tamilarasan

Edward²,

Sarasam

2021

Preprint

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A novel approach called Keeper in LEakage Control Transistor (KLECTOR) is presented in this paper to reduce leakage currents in SRAM architecture. The SRAM is significantly affected by the leakage current during the "standby mode", which is caused by the fabric which has a lower threshold voltage. KLECTOR circuit employs less power consumption by restricting the flow of current through devices of less voltage drops and relies heavily on the self-controlled transistor at the output node. It has been found from the presented results that static (leakage) power in the write operation is reduced to 63% and 69 % for the read operation. This proposed approach is designed and simulated using the Virtuoso, Cadence EDA tool.

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New low-power techniques: Leakage Feedback with Stack & Sleep Stack with Keeper

Cited by 21 publications

References 7 publications

Implementation and modeling of low power sleepy stack SRAM cell

Implementation and modeling of low power sleepy stack SRAM cell

Implementation and Modeling of Low Power Sleepy Stack Sram

KLECTOR: Design of Low Power Static Random-Access Memory Architecture with reduced Leakage Current

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