New insights into the hot carrier degradation (HCD) in FinFET: New observations, unified compact model, and impacts on circuit reliability

Yu, Zhuoqing; Zhang, Jiayang; Wang, Runsheng; Guo, Shaofeng; Liu, Changze; Huang, Ru

doi:10.1109/iedm.2017.8268344

Cited by 51 publications

(32 citation statements)

References 2 publications

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“…The Voltage Acceleration Factor (VAF) associated with the inverse of the time-axis scaling factor (S) is plotted versus VD in Fig.1 (b [33], [34] Similar power-law VAF is obtained across different devices and probing methods in the on-state stress mode, observed for low to moderately high VD range and various VG to VD ratios. It emphasizes the robustness of the unique underlying physical mechanism for on state HCD across technologies and stress VD.…”

Section: Universality Of Hcdmentioning

confidence: 57%

Modeling of HCD Kinetics Under Full V_G – V_D Space, Different Experimental Conditions and Across Different Device Architectures

Sharma

Mahapatra

2020

IEEE J. Electron Devices Soc.

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A SPICE compatible compact modeling framework is discussed for Hot Carrier Degradation (HCD) stress spanning the entire drain (VD) and gate (VG) voltage space and wide range of temperature (T). It can model the HCD time kinetics measured using different methods such as shift in threshold voltage (VT), linear (IDLIN) and saturation (IDSAT) drain current and charge pumping current (ICP), for off and on-state stress. The model is validated using measured data from conventional, Lightly Doped Drain (LDD) and Drain Extended (DE) MOSFETs, FinFETs and Gate All Around Nano Sheet (GAA-NS) FETs. Parametric drift due to Bias Temperature Instability (BTI) stress in the presence of VD is included. Impact due to Self-Heating (SH) and BTI-HCD coupling are considered. SPICE compatibility is shown by cycleby-cycle simulation of various Ring Oscillator (RO) circuits.

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Section: Universality Of Hcdmentioning

confidence: 57%

Modeling of HCD Kinetics Under Full V_G – V_D Space, Different Experimental Conditions and Across Different Device Architectures

Sharma

Mahapatra

2020

IEEE J. Electron Devices Soc.

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“…With continuous channel length scaling, hot carrier degradation (HCD) has emerged as a major reliability issue in FinFETs [ 4 ]. From the trap-based research in HCD, both interface and oxide traps contribute to the overall degradation [ 5 ]. A modified compact model and trap spatial distribution investigations facilitate the accurate characterization of HCD [ 6 , 7 , 8 ].…”

Section: Introductionmentioning

confidence: 99%

Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique

Chang

Wang²,

Yang

et al. 2023

Nanomaterials

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In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs). It is found that increasing GIDL bias from 3 V to 4 V achieves a 114.7% VT recovery ratio from HCD. This over-repair phenomenon of HCD by UFM GIDL is deeply discussed through oxide trap behaviors. When the applied gate-to-drain GIDL bias reaches 4 V, a significant electron trapping and interface trap generation of the fresh device with GIDL repair is observed, which greatly contributes to the approximate 114.7% over-repair VT ratio of the device under worst HCD stress (−2.0 V, 200 s). Based on the TCAD simulation results, the increase in the vertical electric field on the surface of the channel oxide layer is the direct cause of an extraordinary electron trapping effect accompanied by the over-repair phenomenon. Under a high positive electric field, a part of channel electrons is captured by oxide traps in the gate dielectric, leading to further VT recovery. Through the discharge-based multi-pulse (DMP) technique, the energy distribution of oxide traps after GIDL recovery is obtained. It is found that over-repair results in a 34% increment in oxide traps around the conduction energy band (Ec) of silicon, which corresponds to a higher stabilized VT shift under multi-cycle HCD-GIDL tests. The results provide a trap-based understanding of the transistor repairing technique, which could provide guidance for the reliable long-term operation of ICs.

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“…As the device scaled down, however, the carrier energy-based approach became complicated and difficult. Therefore, recent HCD studies of FinFET devices predict lifetime through simple compact modeling based on measurements [9], [10]. In addition, as the channel thickness decreases, the self-heating effect becomes more severe and the influence of temperature on HCD increases [11].…”

Section: Introductionmentioning

confidence: 99%

Analysis on Temperature Dependence of Hot Carrier Degradation by Mechanism Separation

Kim

Hong

Shin

2020

IEEE J. Electron Devices Soc.

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New insights into the hot carrier degradation (HCD) in FinFET: New observations, unified compact model, and impacts on circuit reliability

Cited by 51 publications

References 2 publications

Modeling of HCD Kinetics Under Full V_G – V_D Space, Different Experimental Conditions and Across Different Device Architectures

Modeling of HCD Kinetics Under Full V_G – V_D Space, Different Experimental Conditions and Across Different Device Architectures

Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique

Analysis on Temperature Dependence of Hot Carrier Degradation by Mechanism Separation

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New insights into the hot carrier degradation (HCD) in FinFET: New observations, unified compact model, and impacts on circuit reliability

Cited by 51 publications

References 2 publications

Modeling of HCD Kinetics Under Full VG – VD Space, Different Experimental Conditions and Across Different Device Architectures

Modeling of HCD Kinetics Under Full VG – VD Space, Different Experimental Conditions and Across Different Device Architectures

Insight into over Repair of Hot Carrier Degradation by GIDL Current in Si p-FinFETs Using Ultra-Fast Measurement Technique

Analysis on Temperature Dependence of Hot Carrier Degradation by Mechanism Separation

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Modeling of HCD Kinetics Under Full V_G – V_D Space, Different Experimental Conditions and Across Different Device Architectures

Modeling of HCD Kinetics Under Full V_G – V_D Space, Different Experimental Conditions and Across Different Device Architectures