New high voltage integrated circuits using self-shielding technique

Yamazaki, Tomoyuki; Kumagai, Naoya; Oyabe, K.; Tada, G.; Takeda, H.; Seki, Y.; Sakurai, Kazuo

doi:10.1109/ispsd.1999.764128

Cited by 6 publications

(9 citation statements)

References 3 publications

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“…4(b). does not crossover the ground potential (p-well) parts [21]- [23]. The electric potential of HV interconnection is automatically shielded by spreading the depletion layer in HVJT.…”

Section: New Hvic Concept and Simulation Resultsmentioning

confidence: 99%

A 600 V High-Voltage IC Technique With a New Self-Shielding Structure for High Noise Tolerance and Die Shrink

Yamaji

Jonishi

Tanaka

et al. 2015

IEEE Trans. Electron Devices

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A novel 600 V high-voltage IC (HVIC) featuring a high noise tolerance is proposed. The purpose of the proposed HVIC is to achieve the high noise tolerance without an increase of the fabrication cost. The basic device concept is to arrange a P− separation layer around the high-side control part, which is called a new self-shielding structure, to reduce a hole current injection under the condition of negative transient voltage noise. By applying the new self-shielding structure in the HVIC, more than 3× higher noise tolerance (−95 V/1 µs) and 20% die shrink can be obtained compared with a conventional HVIC, without additional fabrication process. This means the noise tolerance of the fabricated HVIC with proposed structure is high enough to be applied to over 600 V/50-A class power conversion applications. In this paper, the new self-shielding concept of the proposed 600 V-class HVIC is presented with the simulation and experimental results.Index Terms-600 V, high-voltage IC (HVIC), noise tolerance, self-shielding.

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“…4(b). does not crossover the ground potential (p-well) parts [21]- [23]. The electric potential of HV interconnection is automatically shielded by spreading the depletion layer in HVJT.…”

Section: New Hvic Concept and Simulation Resultsmentioning

confidence: 99%

A 600 V High-Voltage IC Technique With a New Self-Shielding Structure for High Noise Tolerance and Die Shrink

Yamaji

Jonishi

Tanaka

et al. 2015

IEEE Trans. Electron Devices

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“…Our proposed device structure has been designed using the high-voltage isolation process based on a self-isolation technique. [1][2][3][4][5] The self-isolation technique is more cost effective than the junction isolation [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22] and dielectric isolation techniques. [23][24][25][26][27][28][29][30] This is because it uses a lessexpensive silicon wafer that is uniformly doped, and it does not need special process steps such as deep diffusion layer and trench formations for the isolation process.…”

Section: Device Conceptmentioning

confidence: 99%

“…High-voltage ICs (HVICs) for driving the gates of power devices arranged in a bridge circuit configuration are intended for use in the development of power supply systems. [1][2][3][4][5] This is because the energy savings in power supply systems can be achieved by using the HVICs. One of the most important parameters of the HVICs to achieve the energy savings is the input=output (I=O) propagation delay time, which dominates the driving performance characteristics of low-side and highside power devices in a bridge circuit.…”

Section: Introductionmentioning

confidence: 99%

Proposal of a new lateral high-voltage n-channel MOS structure with a reduced parasitic output capacitance for a level-shift circuit integrated in 800 V-class high-voltage ICs

Yamaji

Jonishi

Sumida

et al. 2015

Jpn. J. Appl. Phys.

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A new 800 V-class lateral high-voltage n-channel MOS (HVNMOS) structure with a markedly reduced parasitic capacitance (C oss ) has been developed for integration in a high-voltage gate driver IC. In our new HVNMOS, a 40% C oss reduction from that of a conventional HVNMOS can be achieved by using two n-type drift regions divided by a p-type diffusion layer. We have confirmed that a 12% shorter I/O propagation delay time can be achieved by using the new HVNMOS of the high-voltage IC (HVIC) test chip. In this paper, the design concept of the developed HVNMOS is presented with the simulation and experimental results.

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“…High-voltage integrated circuits (HVICs) are devices that have both the smart gate drive and high-voltage isolation functions using a pn junction or a dielectric material. [1][2][3][4][5] Among the several high-voltage isolation structures, the self-isolation structure is realized by simple and costeffective wafer process. [5][6][7] The basic structure and electrical characteristics of key devices, i.e., the high-voltage nchannel metal oxide semiconductor field effect transistor (MOSFET) (HVN) and the high-voltage p-channel MOS-FET (HVP), using a self-shielding technique are described in a previous study.…”

mentioning

confidence: 99%

“…[1][2][3][4][5] Among the several high-voltage isolation structures, the self-isolation structure is realized by simple and costeffective wafer process. [5][6][7] The basic structure and electrical characteristics of key devices, i.e., the high-voltage nchannel metal oxide semiconductor field effect transistor (MOSFET) (HVN) and the high-voltage p-channel MOS-FET (HVP), using a self-shielding technique are described in a previous study. 6) However, there are few reports about the high-voltage p-channel level-shifter using self-isolation.…”

mentioning

confidence: 99%

High-Voltage p-Channel Level Shifter Using Charge-Controlled Self-Isolation Structure

Yamazaki

Kumagai

Nishiura

et al. 2006

jjap

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In this paper, we report an area-effective 600 V p-channel level shifter using a self-isolation structure without the degradation of blocking capability for the first time. To prevent the degradation of high-voltage isolation performance, the charge in a double reduced surface electric field (RESURF) structure is controlled at the border region between a high-voltage p-channel metal oxide semiconductor field effect transistor (MOSFET) and a high-voltage isolation region. Because of a divided p-offset region in the drift region of the high-voltage p-channel MOSFET and the high-voltage isolation region, parasitic current to the ground (GND) terminal through the isolation region can be ignored. By using the new high-voltage p-channel level shifter, a 400 V level shift operation is confirmed.

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New high voltage integrated circuits using self-shielding technique

Cited by 6 publications

References 3 publications

A 600 V High-Voltage IC Technique With a New Self-Shielding Structure for High Noise Tolerance and Die Shrink

A 600 V High-Voltage IC Technique With a New Self-Shielding Structure for High Noise Tolerance and Die Shrink

Proposal of a new lateral high-voltage n-channel MOS structure with a reduced parasitic output capacitance for a level-shift circuit integrated in 800 V-class high-voltage ICs

High-Voltage p-Channel Level Shifter Using Charge-Controlled Self-Isolation Structure

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