New frequency-locked loop based on CMOS frequency-to-voltage converter: design and implementation

Abstract

In this paper, we describe the architecture of a new CMOS fully integrated frequency-locked loop (FLL). The proposed FLL contains a frequency-to-voltage converter (FVC), an operational amplifier (opamp) and a differential voltage-controlled oscillator (VCO). The operation of the proposed circuit is based on frequency comparison of a reference and feedback signals. The architecture of the FVC is built upon capacitors charge redistribution principle, whereas the architecture of the VCO is based on differential delay cells in order to minimize the effect of the power supply and the substrate noise. Simulation carried out with Hspice using the CMOS 0.35-m process shows that the FLL is very fast and operates over a wide frequency range. Two versions of the FLL are reported; the basic architecture could show a static offset due to the two employed FVCs. To alleviate this effect, a second version is proposed to completely eliminate the offset. The area of the proposed FLL is very small, and the design could be easily integrated in the same die together with other analog, digital and mixed-signal blocks. A functional test of five samples of a first version of this FLL proved that the proposed FLL works as expected from simulation results. Examples of the application of the proposed FLL are a high-precision VCO and a frequency synthesizer with true-fractional multiplication and division that does not require binary frequency dividers. Index Terms-Differential-delay cell, frequency-locked loop, frequency-to-voltage converter, phase-locked loop, voltage-controlled oscillator. I. INTRODUCTION A PHASE-LOCKED loop (PLL) circuit is an interesting electronic building block widely used in many integrated applications. It is generally used in systems involving automatic control of frequency or phase, such as communications, frequency synthesis, radar, telemetry, and instrumentation systems. The PLL circuit generates an output signal that tracks an input reference signal. The output signal is synchronized with the input reference signal in frequency as well as in phase. Typically, a PLL is built around a phase detector or phase frequency detector (PFD), a charge pump, a low-pass filter, Manuscript

Process, voltage and temperature compensation in a 1-MHz 130nm CMOS monolithic clock oscillator with 2.3% accuracy

“…They make up a negative feedback loop. The operation of this loop is similar with that of the circuits in Bui and Savaria (2008), Djemouai, Sawan, and Slamani (2001), and it is stable as shown in Bui and Savaria (2008), Djemouai et al (2001). In this loop, the high gain amplifier A forces…”

“…A FVC is widely used in frequency locked loop (Bui and Savaria, 2008;Djemouai et al, 2001). It is usually implemented with charge pump circuits.…”

Frequency-adjustable clock oscillator based on frequency-to-voltage converter

“…It is usually implemented with switched-capacitor circuits. The operation of a FVC is described in detail in [4] and [5]. Here we simply give the expression for V FVC :…”

“…The model object of the FLL is frequency whereas that of the PLL is phase. The FLL model has been discussed sufficiently in [4] and [5].…”

“…Other blocks like the bandgap reference, op amp, LPF, VCO and dividers employ traditional architectures and therefore the design details are ignored in this Letter. A FVC, which transforms a clock signal frequency to a corresponding voltage for processing purposes, is widely used in FLL [4,5]. It is usually implemented with switched-capacitor circuits.…”