New fine line fabrication technology on glass-cloth prepreg without insulating films for PKG substrate

Fujimoto, Daisuke; Yamada, Kunpei; Ogawa, Naoki; Murai, Hikari; Fukai, Hironobu; Kaneko, Youichi; Kato, Masashi

doi:10.1109/ectc.2011.5898542

Cited by 14 publications

(3 citation statements)

References 5 publications

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“…The reliability issue due to their large warpage has prevented the widespread use of coreless substrates. To improve the rigidity and to reduce the warpage of coreless substrates, the use of prepregs as insulating material has been recently reported 9) . However, prepregs could cause skew between differential wirings in high-speed transmissions.…”

Section: Background and Target Of This Studymentioning

confidence: 99%

Low warpage coreless substrate for large-size LSI packages

Kurashina

Mizutani

Koide

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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Due to inadequate rigidity, warpage of coreless substrates is generally large compared to other types of LSI package substrates. Therefore, the most important problem in the application of coreless substrates is warpage reduction during the reflow process. So far, there have been only a limited number of reports on coreless substrates for large-size LSI packages. Moreover, there have been very few examples that discussed substrate layer structure designs for warpage reduction and reliability improvement in the LSI assembly process. In the present study, we focus on developing coreless packages for large-size LSIs. To achieve our goal, we adopted the following development processes.First, we designed analytical models with different layer structures comprising two kinds of materials, and investigated the effect of layer structure on warpage reduction using warpage simulations. Next, we made four kinds of real coreless substrates with layer structures identical to the simulation models, and verified the actual thermal warpage behavior. Finally, we investigated the thermal stress reliabilities of these substrates after LSI mounting.From the results, we found that warpage reduction and reliability enhancement of coreless substrates were realized by arranging the high rigidity materials on the external layers of the substrates.

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Section: Background and Target Of This Studymentioning

confidence: 99%

Low warpage coreless substrate for large-size LSI packages

Kurashina

Mizutani

Koide

et al. 2012

2012 IEEE 62nd Electronic Components and Technology Conference

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“…To improve the rigidity of coreless substrate, the use of prepregs as a dielectric material has been recently reported. [10] Prepreg is adhesion resin sheet that is reinforced by glass cloths, and this material is widely used as a bonding sheet. However, prepregs could cause skew in differential wirings for high-speed transmissions due to the presence of glass cloth, and an explanation figure of skew generation mechanism is shown in Fig.…”

Section: Preparation Of Coreless Substratesmentioning

confidence: 99%

Low Warpage Coreless Substrate for IC Packages

Kurashina

Mizutani

Koide

et al. 2012

Transactions of The Japan Institute of Electronics Packaging

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“…At the same time, they make the substrate thinner, which is very important for today's mobile device applications [3][6] [7]. However, compared to a cored substrate, a coreless substrate is far more mechanically challenged for package design and assembly [1] [8]. The core in a substrate usually has much lower CTE than the build-up dielectric material and the Cu metal layers.…”

Section: Introductionmentioning

confidence: 99%

Coreless substrate with asymmetric design to improve package warpage

Lin

Baloglu

Stratton

2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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Coreless substrates have been used in more and more advanced package designs for their benefits in electrical performance and reduction in thickness. However, coreless substrate causes severe package warpage due to the lack of a rigid and low CTE core. In this paper, both experimental measured warpage data and model simulation data are presented and illustrate that asymmetric designs in substrate thickness direction are capable of improving package warpage when compared to the traditional symmetric design. A few asymmetric design options are proposed, including Cu layer thickness asymmetric design, dielectric layer thickness asymmetric design and dielectric material property asymmetric design. These design options are then studied in depth by simulation to understand their mechanism and quantify their effectiveness for warpage improvement. From the results, it is found that the dielectric material property asymmetric design is the most effective option to improve package warpage, especially when using a lower CTE dielectric in the bottom layers of the substrate and a high CTE dielectric in top layers. Cu layer thickness asymmetric design is another effective way for warpage reduction. The bottom Cu layers should be thinner than the top Cu layers. It is also found that the dielectric layer thickness asymmetric design is only effective for high layer count substrate. It is not effective for low layer count substrate. In this approach, the bottom dielectric layers should be thicker than the top dielectric layers.Furthermore, the results show the asymmetric substrate designs are usually more effective for warpage improvement at high temperature than at room temperature. They are also more effective for a high layer count substrate than a low layer count substrate.

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New fine line fabrication technology on glass-cloth prepreg without insulating films for PKG substrate

Cited by 14 publications

References 5 publications

Low warpage coreless substrate for large-size LSI packages

Low warpage coreless substrate for large-size LSI packages

Low Warpage Coreless Substrate for IC Packages

Coreless substrate with asymmetric design to improve package warpage

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