New dummy design and stiffener on warpage reduction in Ball Grid Array Printed Circuit Board

Cho, Seung-Hyun; Chang, Tienchong; Lee, Joseph Y.; Park, Hyung-Pil; Ko, Young-Bae; gyunmyoung, park

doi:10.1016/j.microrel.2009.10.009

Cited by 12 publications

(6 citation statements)

References 11 publications

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“…However, in many cases, this can be oversimplification since such an approximation by homogenization cannot take pattern continuity into consideration. It is reported that the pattern continuity affects PWB warpage as well as its direction and width [ 8 , 14 ]. It is quite evident that continuation of normal and shear-stress flows dramatically affect overall rigidity.…”

Section: Methodsmentioning

confidence: 99%

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Optimal Dummy Pattern Design Method for PWB Warpage Control Using the Human-Based Genetic Algorithm

Kim¹,

Lee²

2020

Micromachines

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In this work, a method that minimizes printed wiring board (PWB) warpage by dummy pattern design is proposed. This work suggests that dummy patterns are placed on a preset discretized location in the PWB to reduce the warpage. On each discretized candidate area, the dummy pattern can be set or unset. The warpage is numerically simulated based on direct modeling of the as-is PWB patterns to evaluate the warpage alongside the dummy pattern design set. The optimal pattern that minimizes warpage is determined using the human-based genetic algorithm where the objective function is evaluated by the structural simulation. The optimization method is realized in a spreadsheet that allows scripting language with which the input and output files of the simulation tool can be modified and read. Two different cases have been tested and the results show that the method can determine the optimal dummy patterns. The measured and simulated deflections agree well with each other. Moreover, it has been shown that certain dummy pattern designs that should reduce the warpage can be sought by the optimization.

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Section: Methodsmentioning

confidence: 99%

“…Such copper patterns are called dummy patterns and have been widely utilized to control the warpage. Changing dummy patterns does not affect the circuit performance and is one of the best ways the PWB industry can select [ 7 , 8 ]. There are some other techniques that can remedy warpage.…”

Section: Introductionmentioning

confidence: 99%

Optimal Dummy Pattern Design Method for PWB Warpage Control Using the Human-Based Genetic Algorithm

Kim¹,

Lee²

2020

Micromachines

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“…Package warpage has been studied by many researchers in the past [1][2][3][4][5][6]. Many methods have been developed to predict warpage as it is a critical problem for the microelectronics industry.…”

Section: Warpage Prediction Strategiesmentioning

confidence: 99%

“…One of the solutions to realize a high level of silicon integration is by fabricating high density wiring substrate with sequential buildup technology. However, during sequential processing of multi-layered substrates, significant warpage arises due to the temperature gradients and coefficient of thermal expansion (CTE) mismatch among the different materials [1][2][3]. The magnitude of warpage depends on mismatch in material properties, dimensions and sequencing of the layers, process, processing conditions, size and density of copper and other embedded components.…”

Section: Introductionmentioning

confidence: 99%

Development of numerical modeling approach on substrate warpage prediction

Biswas¹,

Liu²,

Zhang

et al. 2012

2012 IEEE 14th Electronics Packaging Technology Conference (EPTC)

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Prediction and reduction of substrate warpage is very important to enhance assembly yield, and to improve reliability in the microelectronic packaging industry. Modeling the copper trace pattern of a packaging substrate is a difficult and time consuming task. Modeling of these patterns are often too complex for FEM to model exactly, so steps are taken to reduce the number of elements and computation time necessary to model trace patterns with FEM. An often used approach is to use micromechanics considerations to find effective material properties for layers of mixed copper and dielectric material. This approach yields isotropic properties for trace pattern layers based on the percentages of copper and dielectric material present in that layer. But that method is not so accurate to use it always. So, a new approach based on copper percentage at each sub region of a metal layer is proposed.It is found that Cu distribution has a major effect on substrate warpage although average Cu percentages for top and bottom Cu layers are same. By proper distribution of Cu areas on a plane, warpage of the package can be modified. Simulation results of substrate warpage obtained using this cell model are much close to the experimental results.. This method is less time consuming and requires less computation time than the actual model with details Cu traces. IntroductionThe current technology focuses on ultra-thin multi-layered wiring boards with increased performances. One of the solutions to realize a high level of silicon integration is by fabricating high density wiring substrate with sequential buildup technology. However, during sequential processing of multi-layered substrates, significant warpage arises due to the temperature gradients and coefficient of thermal expansion (CTE) mismatch among the different materials [1-3]. The magnitude of warpage depends on mismatch in material properties, dimensions and sequencing of the layers, process, processing conditions, size and density of copper and other embedded components.The objective of this paper is to accurately predict multilayered substrate warpage taking into consideration the amount of copper traces in each metal layer as well as subregion on each metal layer, and to perform experimental measurement to validate such models. Even with the advances in modeling methodologies, the prediction of warpage based on models alone is not acceptable. Complicated structures such as package substrates and uncertainty involved with accurate material properties require experimental validation to be carried out to show that the model predictions are accurate.

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“…Warpage formation is generally known to arise from coefficient of thermal expansion (CTE) mismatch between multilayered materials with different properties. The different properties of each PCB layer will yield different expansion rates, which will lead to extremely high warpage formation under the reflow temperature (Cho et al , 2010). The presence of significant warpage will further induce opened solder joint risks, solder joint collapse for flip-chip BGAs (FCBGAs) and so on.…”

Section: Introductionmentioning

confidence: 99%

Dynamic warpage simulation of molded PCB under reflow process

Sek

Abdullah

et al. 2021

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Purpose This study aims to simulate molded printed circuit board (PCB) warpage behavior under reflow temperature distribution. Simulation models are used to estimate dynamic warpage behavior for different form factor sizes. Design/methodology/approach This study analyzes warpage during the reflow process. The shadow moiré experiment methodology is used to collect data on the dynamic warpage performance of a model with a form factor of 10mm × 10mm × 1mm. The temperature profile with heating from 25°C to 300°C at intervals of 50°C is used, and the sample is made to undergo a cooling process until it reaches the room temperature. Subsequently, ANSYS static structural simulation is performed on similar form factor models to ascertain the accuracy of the simulation results. Findings Results show that the deformation and total force induced by coefficient of thermal expansion (CTE) mismatch are examined based on the warpage performance of models with different sizes, that is, 45mm × 45mm × 1mm and 45mm × 15mm × 1mm. Compared with the experimental data, the simulated modeling accuracy yields a less than 5% deviation in the dynamic warpage prediction at a reflow temperature of 300°C. Results also reveal that the larger the model, the larger the warpage changes under the reflow temperature. Research limitations/implications The simulated warpage is limited to the temperature and force induced by CTE mismatch between two materials. The form factor of the ball-grid array model is limited to only three different sizes. The model is assumed to be steady, isothermal and static. The simulation adopts homogenous materials, as it cannot accurately model nonhomogeneous multilayered composite materials. Practical implications This study can provide engineers and researchers with a profound understanding of molded PCB warpage, minimal resource utilization and the improved product development process. Social implications The accurate prediction of molded PCB warpage can enable efficient product development and reduce resources and production time, thereby creating a sustainable environment. Originality/value The literature review points out that warpage in various types of PCBs was successfully examined, and that considerable efforts were exerted to investigate warpage reduction in PCB modules. However, PCB warpage studies are limited to bare PCBs. To the best of the authors’ knowledge, the examination of warpage in a molded PCB designed with a molded compound cover, as depicted in Figure 3, is yet to be conducted. A molded compound provides strong lattice support for PCBs to prevent deformation during the reflow process, which is a topic of considerable interest and should be explored.

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New dummy design and stiffener on warpage reduction in Ball Grid Array Printed Circuit Board

Cited by 12 publications

References 11 publications

Optimal Dummy Pattern Design Method for PWB Warpage Control Using the Human-Based Genetic Algorithm

Optimal Dummy Pattern Design Method for PWB Warpage Control Using the Human-Based Genetic Algorithm

Development of numerical modeling approach on substrate warpage prediction

Dynamic warpage simulation of molded PCB under reflow process

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