New CMOS Compatible Realizations of Grounded/Floating L, C Multiplier and FDNC Simulators

Kumar, Atul; Chaturvedi, Bhartendu; Jagga, Shafali

doi:10.1007/s00034-022-02207-z

Cited by 9 publications

(1 citation statement)

References 33 publications

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“…CM circuits can be classified as grounded [1][2][3][4][5][6][7][8] and floating [9][10][11][12][13][14][15][16][17][18] according to the type of the simulated capacitance, and positive [1][2][3][4][5][6][7] and negative [19][20][21][22][23][24][25][26][27][28] according to the value of the simulated capacitance.…”

Section: Introductionmentioning

confidence: 99%

Design of Lossless Negative Capacitance Multiplier Employing a Single Active Element

Vahbeh,

Özer,

Kaçar

2024

Electronics

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In this paper, a new negative lossless grounded capacitance multiplier (GCM) circuit based on a Current Feedback Operational Amplifier (CFOA) is presented. The proposed circuit includes a single CFOA, four resistors, and a grounded capacitor. In order to reduce the power consumption, the internal structure of the CFOA is realized with dynamic threshold-voltage MOSFET (DTMOS) transistors. The effects of parasitic components on the operating frequency range of the proposed circuit are investigated. The simulation results were obtained with the SPICE program using 0.13 µm IBM CMOS technology parameters. The total power consumption of the circuit was 1.6 mW. The functionality of the circuit is provided by the capacitance cancellation circuit. PVT (Process, Voltage, Temperature) analyses were performed to verify the robustness of the proposed circuit. An experimental study is provided to verify the operability of the proposed negative lossless GCM using commercially available integrated circuits (ICs).

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Section: Introductionmentioning

confidence: 99%

Design of Lossless Negative Capacitance Multiplier Employing a Single Active Element

Vahbeh,

Özer,

Kaçar

2024

Electronics

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VCII‐Based Immittance Simulators: Generalized Parallel Configurations

Shrivastava,

Bhaskar,

Kumar

2024

Circuit Theory & Apps

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In this paper, four new generalized configurations of grounded parallel‐type immittance simulators are proposed. These circuits implement parallel resistor–inductor (RL), parallel resistor–capacitor (RC), parallel capacitor–frequency‐dependent negative resistance (CD), and capacitance multiplier configurations utilizing only two second‐generation voltage conveyors (VCII±) as active elements along with three impedances, without the need for specific matching conditions. The applicability of the proposed parallel RL and capacitance multiplier configurations as a second‐order high‐pass filter (HPF) and a first‐order low‐pass filter (LPF), respectively, is also demonstrated. These applications illustrate the versatility and utility of the proposed structures. Frequency, transient, and Monte Carlo analysis utilizing the CMOS VCII± in the SPICE simulation tool have also been performed to validate the feasibility of the presented circuits. Further validation is carried out through layout design in Cadence Virtuoso, employing 0.18‐μm CMOS technology. Both presimulation and postsimulation results are presented for a thorough assessment of the proposed circuits. Also, the claimed theory is verified by experimental results based on the VCII implementation with commercially available IC AD844.

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Enhancement of multiplication factor of capacitor using single current follower differential input transconductance amplifier

Raj,

Shrivastava,

Bhaskar

et al. 2024

Int J Numerical Modelling

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This paper presents a new circuit approach to realize a capacitance multiplier circuit with positive and negative multiplication factors. Based on this approach, two new implementations of positive and negative grounded capacitance multiplier (GCM) circuits are proposed, which utilize only one current follower differential input transconductance amplifier (CFDITA), in conjunction with only one resistor and one virtually grounded capacitor. The presented GCM circuits can enhance a low capacitance value to a very high value (used in low frequency applications), up to 9202 times its original value. An important aspect of the proposed circuits involves designing a lossy parallel inductor circuit by interchanging the passive elements (RC:CR transformation) with each other. The obtained value of the capacitance and inductance can be controlled independently and electronically through the transconductance of CFDITA. The practical usability of the suggested circuits as first and second order filters is discussed. The functionality of the proposed GCM circuits is validated using CMOS CFDITA implemented with 180 nm TSMC technology parameters. Experimental verification of the proposed circuits and application examples is reinforced through the utilization of CFDITA implemented with readily available ICs AD844 and LM13700. These outcomes emphasize the dependability of the suggested circuits.

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New CMOS Compatible Realizations of Grounded/Floating L, C Multiplier and FDNC Simulators

Cited by 9 publications

References 33 publications

Design of Lossless Negative Capacitance Multiplier Employing a Single Active Element

Design of Lossless Negative Capacitance Multiplier Employing a Single Active Element

VCII‐Based Immittance Simulators: Generalized Parallel Configurations

Enhancement of multiplication factor of capacitor using single current follower differential input transconductance amplifier

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