New Approach to VLSI Buffer Modeling, Considering Overshooting Effect

Improving Analytical Delay Modelingfor CMOS Inverters

“…In [24], Uebel and Bampi propose an exploit fitting parameters to improve accuracy of RC modeling. In [25], Mehri et al analytically obtain average values for the transistor resistance considering the influence of input transition time. However, assuming similar input and output transitions and neglecting SCC.…”

“…As shown in Table 1, the inverter delay estimation methods proposed in [1]- [4] [25]. In order to correct inadequate modeling, fitting parameters are often employed [12][15]- [17][21] [24].…”

“…In order to correct inadequate modeling, fitting parameters are often employed [12][15]- [17][21] [24]. Furthermore, some approaches do not provide explicit delay formulation for the entire range of input transition time [8][12] [13][20] [25]. The inverter delay model proposed in this work aims to overcome these drawbacks.…”

“…Tout50 is found by calculating the total charge drained by NMOS transistor (Qn), from the beginning of input transition until Tout50: (22) where Tvth n is the time instant when the input reaches Vth n . Solving (21), Qn is found as: (23) Defining Δt as the time elapsed between Tvth n and Tout50 (i.e., Δt = Tout50 -Tvth n ), and knowing that Vth n = (Tvth n .Vdd)/Tin, (23) can be written as follows: (24) Since Qtot is equal to Qn, from ( 20) and ( 23), it follows: (25) Thus, the final value of Tout50 in the slow input domain is given by:…”

“…Among other applications, inverter chains (buffers) are used in the distribution of clock signals and to drive large loads as those occurring in I/O pads. Because the analysis and optimization of buffers relying on electrical simulations tends to be a very time consuming task, many works have proposed analytical delay models targeting the CMOS inverter [1]- [25], and explored such models in buffer design optimization [34]- [36].…”