New approach to design D-flip flop and two bit down counter using optical micro-ring resonator for high speed data processing

Abstract

Optical switches play a key role in the field of high-speed optical fiber communication and signal processing. Present work shows the design and implementation of D-flip flop and a two-bit optical counter using optical micro ring resonator (OMRR). The design of the proposed model is developed by considering nonlinear material-based resonators. Here, three OMRR based optical switches are used to design the D-flip flop circuit thereafter two-bit optical counter is implemented using the modeled D-flip flop. The mathematical model of the D-flip flop circuit is provided in the Z-domain by unit delay signal processing approach. The effectiveness of the proposed D flip flop and two-bit down counter circuit is described in the present work. The accuracy and feasibility of the circuits are determined by estimating various performance parameters during simulation.

Review on all-optical logic gates: design techniques and classifications – heading toward high-speed optical integrated circuits

“…169 A design of AO-D FF and 2-bit down counter was proposed based on nonlinear effect in optical MRR to achieve satisfactory performance metrics. 170 An AO-counter based on RS FF and AND gate was presented using cascaded stages of SOA fiber laser utilizing FWM effect. 171 Twophoton absorption effect in silicon MRR was used to achieve the design of CMOS compatible AO-RS FF and 2-bit counter at 45 Gbps.…”

Implementation of all-optical synchronous and asynchronous binary up counters using silicon micro-ring resonator

“…A Johnson counter was designed by deploying SOA-based D FFs with a maximum speed of 10 Gbps 13 . The 2-bit synchronous up and down counters were designed using MRRs and were analyzed in the z-domain in which the photoconductive sample and hold circuit was used to convert the optical signal into an electrical signal and the electrical signal was again converted into the optical signal 14 , 15 . The maximum speed of operation of these counters is limited to 55 to 72 Gbps, and a high control power of 10 mW is also required.…”

“…A 2-bit asynchronous down counter was implemented in Ref. 15 employing 6 MRRs with an operational speed of 55 Gbps and a required pump power of 10 mW. An implementation of a 2-bit asynchronous ripple down counter was presented in Ref.…”