Neuron-MOS-based Dynamic Circuits for Multiple-Valued Logic

Hang, Guoqiang; Yang, Yang; Zhang, Danyan; Li, Xiaohua

doi:10.1109/cis.2014.178

Cited by 4 publications

(3 citation statements)

References 12 publications

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“…Compared with TNOR designed by traditional methods, this design has the advantages of low power consumption and low delay. In addition, researches on dynamic ternary logic circuits [28][29][30] with significant operational advantage in VLSI are also being carried out successively. In recent years, with the continuous development of semiconductor materials, researchers have adopted different technical solutions to design a standard ternary inverter based on the traditional CMOS binary inverter structure, which realizes the three-state operation.…”

Section: Design Of Ternary Logic Gates Based On Mosfetsmentioning

confidence: 99%

A review on the design of ternary logic circuits*

Wang

Dong

2021

Chinese Phys. B

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A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity, power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.

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Section: Design Of Ternary Logic Gates Based On Mosfetsmentioning

confidence: 99%

A review on the design of ternary logic circuits*

Wang

Dong

2021

Chinese Phys. B

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“…A neuron-MOS transistor is a novel functional transistor with multiple-input gates, and is characterized by a variable threshold voltage achieved by controlling the voltages of the multiple-input gates [8]. This feature is most suitable to use in constructing voltage-mode MVL circuits [9,10,11]. Its variable threshold voltage nature is also one of the most attractive characteristics for Schmitt trigger implementation.…”

Section: Introductionmentioning

confidence: 99%

Voltage-Mode Multi-Valued Schmitt Trigger with Neuron-MOS Transistors

Hang

Zhou

Zhang

et al. 2013

AMM

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A novel design scheme of multiple-valued Schmitt trigger using neuron-MOS transistors is presented. By controlling the voltages of the multiple-input gates, the neuron-MOS literal circuits with hysteresis characteristics are firstly designed. Then, the transmission switches used to pass quaternary signal are controlled by the outputs of these literal circuits to realize three hysteresis loops of quaternary Schmitt circuit. The benefit of the proposed quaternary Schmitt trigger is that the circuit can be fabricated by standard CMOS process with a 2-ploy layer. The three hysteresis loops are fully adjustable by sizing the ratio of capacitive coupling coefficients. The effectiveness of the proposed Schmitt trigger has been validated by HSPICE simulation results with TSMC 0.35μm 2-ploy 4-metal CMOS technology, and the discrepancy of hysteresis values between the simulated and theoretical results is smaller than 6%.

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“…Since then, numerous electronic devices have been explored to realize a simple ternary architecture or further multivalued logic. These include resonant tunneling diodes, resonant tunneling transistors, neuron MOS transistors, SETs, CNT FETs, and quantum dot FETs1620212223242526. Resonant tunneling diode had to use multiple devices to generate multiple states, and the fabrication processes using compound semiconductors were too complex to be competitive with silicon technology2223.…”

mentioning

confidence: 99%

Demonstration of Complementary Ternary Graphene Field-Effect Transistors

Kim

Noh

et al. 2016

Sci Rep

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Strong demand for power reduction in state-of-the-art semiconductor devices calls for novel devices and architectures. Since ternary logic architecture can perform the same function as binary logic architecture with a much lower device density and higher information density, a switch device suitable for the ternary logic has been pursued for several decades. However, a single device that satisfies all the requirements for ternary logic architecture has not been demonstrated. We demonstrated a ternary graphene field-effect transistor (TGFET), showing three discrete current states in one device. The ternary function was achieved by introducing a metal strip to the middle of graphene channel, which created an N-P-N or P-N-P doping pattern depending on the work function of the metal. In addition, a standard ternary inverter working at room temperature has been achieved by modulating the work function of the metal in a graphene channel. The feasibility of a ternary inverter indicates that a general ternary logic architecture can be realized using complementary TGFETs. This breakthrough will provide a key stepping-stone for an extreme-low-power computing technology.

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Neuron-MOS-based Dynamic Circuits for Multiple-Valued Logic

Cited by 4 publications

References 12 publications

A review on the design of ternary logic circuits*

A review on the design of ternary logic circuits*

Voltage-Mode Multi-Valued Schmitt Trigger with Neuron-MOS Transistors

Demonstration of Complementary Ternary Graphene Field-Effect Transistors

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