Neuromorphic VLSI Models of Selective Attention: From Single Chip Vision Sensors to Multi-chip Systems

Abstract

Biological organisms perform complex selective attention operations continuously and effortlessly. These operations allow them to quickly determine the motor actions to take in response to combinations of external stimuli and internal states, and to pay attention to subsets of sensory inputs suppressing non salient ones. Selective attention strategies are extremely effective in both natural and artificial systems which have to cope with large amounts of input data and have limited computational resources. One of the main computational primitives used to perform these selection operations is the Winner-Take-All (WTA) network. These types of networks are formed by arrays of coupled computational nodes that selectively amplify the strongest input signals, and suppress the weaker ones. Neuromorphic circuits are an optimal medium for constructing WTA networks and for implementing efficient hardware models of selective attention systems. In this paper we present an overview of selective attention systems based on neuromorphic WTA circuits ranging from single-chip vision sensors for selecting and tracking the position of salient features, to multi-chip systems implement saliency-map based models of selective attention.

Characterization and Compensation of Network-Level Anomalies in Mixed-Signal Neuromorphic Modeling Platforms

“…So far there have only been few attempts at realizing highly configurable hardware emulators Indiveri et al (2006); Vogelstein et al (2007); Rocke et al (2008); Schemmel et al (2010); Furber et al (2012). This approach alone, however, does not completely resolve the computational bottleneck of software simulators, as scaling neuromorphic neural networks up in size becomes non-trivial when considering bandwidth limitations between multiple interconnected hardware devices Costas-Santos et al (2007); Berge and Häfliger (2007); Indiveri (2008); Fieres et al (2008); Serrano-Gotarredona et al (2009).…”

A wafer-scale neuromorphic hardware system for large-scale neural modeling

“…This is an especially useful property considering the reliability concerns of future CMOS generations [3]. In addition, by using only a few transistors to emulate the neuron's differential equations compared to several millions involved in the same task while solving these equations numerically on a microprocessor core, the power consumption is reduced by several orders of magnitude [4]. Due to the inherent continuous time operation of a physical model it is much faster than the numerical approach for all but the most simple network configurations.…”

Discriminating Multiple Nearby Targets Using Single-Ping Ultrasonic Scene Mapping

“…The classifier can be implemented as a winner-takes-all (WTA) circuit. Indiveri mentions a power consumption of 1.1 mW for a sensor which utilizes a 676 input WTA [35], which is far above the which we need; thus, classification can be done using under 1.1 mW. Using these power figures for the front end, filtering and classification provide maximum power estimate well under 20 mW.…”