Neuromorphic photonic technologies and architectures: scaling opportunities and performance frontiers [Invited]

Abstract

We review different technologies and architectures for neuromorphic photonic accelerators, spanning from bulk optics to photonic-integrated-circuits (PICs), and assess compute efficiency in OPs/Watt through the lens of a comparative study where key technology aspects are analyzed. With an emphasis on PIC neuromorphic accelerators, we shed light onto the latest advances in photonic and plasmonic modulation technologies for the realization of weighting elements in training and inference applications, and present a recently introduced scalable coherent crossbar layout. Finally, we stress that current technologies face challenges endowing photonic accelerators with compute efficiencies in the PetaOPs/W, and discuss future implementation pathways towards improving performance.

Optics-informed neural networks towards accelerating linear operations

“…With current projections forecasting that the computational power requirements will double every 5-6 months [2], the way to the rescue was initially sought in innovative electronic AI hardware architectures, including neuromorphic [3]- [6] and analog-in-Memory Computing (AiMC) [7]. Sculpturing, however, an AI hardware roadmap around electronics implies inherent energy constraints due to the speed and power limits of the electronic interconnects inside the circuits [8]- [10]. This deadlock has driven the emergence of neuromorphic photonics that were theoretically predicted to allow for orders of magnitude improvements in energy and size efficiencies compared to electronic AI platforms [11]- [13].…”

Neuromorphic silicon photonics with 50 GHz tiled matrix multiplication for deep-learning applications

“…Yet, as transistor scaling is stagnating, 10 a high number of alternative emerging technologies have been investigated toward boosting energy efficiency and performance scaling, e.g., optoelectronic memristors, 11 – 15 nanophotonics, 16 , 17 and spintronics, 18 , 19 with brain-inspired photonic accelerators forming one of the key candidate platforms for future AI computing engines due to their inherent credentials to support time-of-flight latencies and terahertz bandwidths 20 , 21 . Remarkable progress has been witnessed during the last five years in the field of neuromorphic photonics across all necessary constituent technology blocks, including MVM photonic architectures, 17 , 22 – 28 individual photonic computational elements, 29 – 32 nonlinear activations, 33 – 36 and photonic hardware-aware training models 37 , 38 . All these demonstrations have highlighted the potential for energy-efficient and high-speed DNNs by utilizing low-speed weight encoding technologies and a rather small amount of neurons, validating their credentials to support inference within small scale neural network (NN) topologies that can fit in a practical silicon photonic (SiPho) chip.…”

Implementation of input correlation learning with an optoelectronic dendritic unit

“…Novel nanoscale electronic devices based on memristive properties [9][10][11][12][13][14], spintronics [15,16] or organic electronics [17] have emerged as possible candidates for synapses or neurons in neuromorphic computing systems, enabling ultra-low power consumption. Photonic platforms have also adopted neuromorphic approaches for efficient computing over the last decade [18,19]. There is a plethora of works that explore diverse photonic platforms for neuromorphic computing, such as optoelectronic or fiber-based with temporal encoding [20][21][22][23][24], free-space optics with spatial encoding [25,26], or photonic integrated circuits [19,27,28].…”

“…Photonic platforms have also adopted neuromorphic approaches for efficient computing over the last decade [18,19]. There is a plethora of works that explore diverse photonic platforms for neuromorphic computing, such as optoelectronic or fiber-based with temporal encoding [20][21][22][23][24], free-space optics with spatial encoding [25,26], or photonic integrated circuits [19,27,28]. Some proposals aimed at addressing challenges in analog computing [20,21,29], while others aimed at implementing spiking networks with timedependent plasticity (STDP) [22,23,30,31].…”