Networks on Chips

Benini, Luca; Micheli, Giovanni De

doi:10.1016/b978-012385251-9/50017-7

Cited by 23 publications

(10 citation statements)

References 43 publications

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“…On the right, we have the hardware platform with the four computational resources r 1 to r 4 , and four routers r 5 to r 8 . The architecture follows a grid-like network-on-chip (NoC [11]) structure. This is not necessary for our formalization but is usually assumed and present in our benchmark instances.…”

Section: System Synthesis Problemmentioning

confidence: 99%

Evolutionary System Design with Answer Set Programming

et al. 2023

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We address the problem of evolutionary system design (ESD) by means of answer set programming modulo difference constraints (AMT). The goal of this design approach is to synthesize new product variants or generations from existing products. We start by formalizing the underlying system synthesis problem and design space exploration process, which consists of finding the Pareto front with respect to latency, cost, energy, and similarity measures between the two designs. We then present AMT-based encodings to capture all of these aspects. The idea is to use plain ASP for conflict detection and resolution and for routing and to use difference constraints for scheduling. Moreover, we propose a new approach for expressing the similarity that we use at three alternative levels of AMT-based design space exploration, namely, at the strategic, heuristic, and objective levels, which is performed to guide the exploration towards designs of high interest. Last but not least, we systematically evaluate the emerging techniques empirically and identify the most promising AMT techniques.

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Section: System Synthesis Problemmentioning

confidence: 99%

Evolutionary System Design with Answer Set Programming

et al. 2023

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“…Packet-switched Networks-on-Chip (NoCs) are considered as promising solution to the interconnection problem in MultiProcessor Systems-on-Chip (MPSoC) [1], [3]. Examples like QNoC [2], AEthereal [4] or Nostrum [13] even support Quality-of-Service (QoS) mechanisms, i.e.…”

Section: Introductionmentioning

confidence: 99%

Guaranteed service virtual channel allocation in NoCs for run-time task scheduling

Winter

Fettweis

2011

2011 Design, Automation &Amp; Test in Europe

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Quality-of-Service becomes a vital requirement in MPSoCs with NoCs. In order to serve them NoCs provide guarantees for latency, jitter and bandwidth by virtual channels. But the allocation of these guaranteed service channels is still an important question. In this paper we present and evaluate different realizations of a central hardware unit which allocates at run-time guaranteed service virtual channels providing QoS in packet-switched NoCs. We evaluate their performance in terms of allocation success, compare it to distributed channel setup techniques for different NoC sizes and traffic scenarios and analyze the required hardware area consumption. We find centralized channel allocation to be very suitable for our run-time task scheduling programming model.

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“…These on-chip networks are necessary as the performance of the classic shared bus cannot scale to tens of cores. Various interconnection networks have been studied [3][4][5]. Among popular networks are the Mesh and Torus [4], Cube-Connected Cycles [6], and Fat Tree [7].…”

Section: Introductionmentioning

confidence: 99%

Throughput and latency analysis of the Spidergon-Donut interconnection network

Sibai

El-Moursy

Mohamed

2012

2012 International Conference on Innovations in Information Technology (IIT)

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The Spidergon-Donut on-chip interconnection network was proposed to interconnect the cores of a 1000+ core chip. In this paper, we derive a queueing model for the Spidergon-Donut, and analyze its throughput and latency in comparison with the commercial Spidergon network on which it is based. Results indicate that the Spidergon-Donut throughput is 3-5 times larger than that of the Spidergon network, for 32-4096 cores and the Spidergon-Donut significantly outperforms the Spidergon in network latency under moderate to large traffic rates. Furthermore, for 1K cores, the average distance of the Spidergon-Donut is one tenth that of the Spidergon.

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Networks on Chips

Cited by 23 publications

References 43 publications

Evolutionary System Design with Answer Set Programming

Evolutionary System Design with Answer Set Programming

Guaranteed service virtual channel allocation in NoCs for run-time task scheduling

Throughput and latency analysis of the Spidergon-Donut interconnection network

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