Networks on Chip as Hardware Components of an OS for Reconfigurable Systems

Marescaux, Théodore; Mignolet, J.-Y.; Bartic, T. Andrei; Moffat, W.; Verkest, D.; Vernalde, Serge; Lauwereins, Rudy

doi:10.1007/978-3-540-45234-8_58

Cited by 52 publications

(47 citation statements)

References 3 publications

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“…Instead of connecting the modules using dedicated routing wires, they are connected to a network that route packets among them. Maresceaux et al [4] proposed the use of a NoC communication infrastructure as a component of an operating system for reconfigurable systems. However, their NoC approache supports only fixed processing modules defined as tile on the chip at compile time.…”

Section: Related Workmentioning

confidence: 99%

A Dynamic NoC Approach for Communication in Reconfigurable Devices

Bobda

Majer

Koch

et al. 2004

Field Programmable Logic and Application

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Abstract.A concept for solving the communication problem among modules dynamically placed on a reconfigurable device is presented. Based on a dynamic network-on-chip (DyNoC) communication infrastructure, components placed at run-time on a device can mutually communicate. A 4x4 dynamic network-on-chip communication infrastructure prototype, implemented in an FPGA occupies only 7% of the device area and can be clocked at 391 MHz.

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Section: Related Workmentioning

confidence: 99%

A Dynamic NoC Approach for Communication in Reconfigurable Devices

Bobda

Majer

Koch

et al. 2004

Field Programmable Logic and Application

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“…a ring of active network elements exists around each placed module at all times. While in a static NoC [4,9], each router always has four active neighbor router nodes 2 , this is not always the case in the DyNoC presented for the first time in [5]. Whenever a module is placed on the device, it covers all routers in its area.…”

Section: Network Accessmentioning

confidence: 99%

Packet Routing in Dynamically Changing Networks on Chip

Majer

Bobda

Ahmadinia

et al.

19th IEEE International Parallel and Distributed Processing Symposium

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On-line routing strategies for communication in a dynamic network on chip (DyNoC) environment are presented. The DyNoC has been presented as a medium supporting communication among modules which are dynamically placed on a reconfigurable device at run-time. Using simulation, we compare the performance of an adaptive Qrouting algorithm to the well known XY-routing strategy. Both algorithms are adapted to support communication on the DyNoC which is equivalent to routing on meshes with obstacles. In our experiments, Q-routing proves its performance under varying network load while using only local information for its routing decisions.

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“…circuit level), several approaches have been implemented in FPGAs. In [8] and [2], NoCs with a mesh-based topology and packet-switching as communication mechanism shows the effectiveness of NoC. Also, other NoC architectures (e.g.…”

Section: Related Workmentioning

confidence: 99%

“…Hence, the NoC paradigm implies a new complex design and research topic for on-chip communication. Presently, concrete options for NoC topologies and interfaces have been proposed at different levels of abstraction [10], [7], [9] and some even implemented onto FPGAs for functional validation [8], [2]. Nevertheless, these different physical implementations onto Field Programmable Gate Arrays (FPGAs) are limited in flexibility and do not enable a full test of different actual realizations of NoC on silicon.…”

Section: Introductionmentioning

confidence: 99%

A Novel Approach for Network on Chip Emulation

Genko

Atienza²,

Micheli³

et al.

2005 IEEE International Symposium on Circuits and Systems

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Abstract-Current Systems-On-Chip execute applications that demand extensive parallel processing. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solutions. NoCs can have regular or ad hoc topologies, and functional validation is essential to assess their correctness and performance. In this paper, we present a flexible emulation environment implemented on an FPGA that is suitable to explore, evaluate and compare a wide range of NoC solutions with a very limited effort. Our experimental results show a speed-up of four orders of magnitude with respect to cycle-accurate HDL simulation, while retaining cycle accuracy. With our emulation framework, designers can explore and optimize a range of solutions, as well as characterize quickly performance figures.

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Networks on Chip as Hardware Components of an OS for Reconfigurable Systems

Cited by 52 publications

References 3 publications

A Dynamic NoC Approach for Communication in Reconfigurable Devices

A Dynamic NoC Approach for Communication in Reconfigurable Devices

Packet Routing in Dynamically Changing Networks on Chip

A Novel Approach for Network on Chip Emulation

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