Negative Capacitance as Universal Digital and Analog Performance Booster for Complementary MOS Transistors

Abstract

Boltzmann electron energy distribution poses a fundamental limit to lowering the energy dissipation of conventional MOS devices, a minimum increase of the gate voltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-source current at 300 K. Negative Capacitance (NC) in ferroelectric materials is proposed in order to address this physical limitation of CMOS technology. A polarization destabilization in ferroelectrics causes an effective negative permittivity, resulting in a differential voltage amplification and a reduced subthreshold swing when integrated into the gate stack of a transistor. The novelty and universality of this approach relate to the fact that the gate stack is not anymore a passive part of the transistor and contributes to signal amplification. In this paper, we experimentally validate NC as a universal performance booster: (i) for complementary MOSFETs, of both n- and p-type in an advanced CMOS technology node, and, (ii) for both digital and analog significant enhancements of key figures of merit for information processing (subthreshold swing, overdrive, and current efficiency factor). Accordingly, a sub-thermal swing down to 10 mV/decade together with an enhanced current efficiency factor up to 10 5 V −1 is obtained in both n- and p-type MOSFETs at room temperature by exploiting a PZT capacitor as the NC booster. As a result of the subthreshold swing reduction and overdrive improvement observed by NC, the required supply voltage to provide the same on-current is reduced by approximately 50%.

Stepwise internal potential jumps caused by multiple-domain polarization flips in metal/ferroelectric/metal/paraelectric/metal stack

“…It directly indicates that the V int gain is associated with the polarization flip in a FE layer. This fact is critically important from the viewpoint that it is beyond the qualitative observation in the similar measurements reported recently 16,37 . It is worthy of mentioning that the measured voltage was time dependent and it gradually changed due to the finite resistance in FE and PE layers as mentioned above.…”

“…As a matter of fact, the bias dependence of semiconductor capacitance makes hysteresis-free FET more difficult. Thus, hysteresis is seen in most of the steep-SS FETs reported up to now 16,22,23 . More detailed discussion of the hysteresis is shown in Supplementary Fig.…”

“…Several models of quasi-static NC associated with domain wall motion in a multiple-domain system have been also proposed [9][10][11][12][13] . Meanwhile, steep SS values have been demonstrated by incorporating FE/PE gate stacks into FETs with various FE materials [14][15][16] , various channel materials 15,[17][18][19] and various FET structures 14,[20][21][22][23][24] .…”

“…A direct way to examine the actual FE effect in FE/PE stack is to investigate the voltage at the internal node, V int , between FE and PE layers in DC mode, which makes possible of the direct correlation of V int with SS in FET. In fact, a couple of works on internal potential measurement have been reported, but they have only qualitatively discussed about this issue, resulting that a consistent model could not been provided 16,37 . We have suspected it might be due to experimental difficulties of measuring the internal potential in FE/PE stack.…”

Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect

“…Although we do not know how Q m is related to x, we know the relation between Q m and V ch from (10) and (11) in depletion and accumulation modes respectively. In addition, from the drain current I ds relationship, dx and V ch are linked as follows By substituting (17) in (16) the integral in space turns into an integral over the potential of the channel from the source (S) to the drain (D)…”