Negative bias temperature instability in p-channel power VDMOSFETs: recoverable versus permanent degradation

Danković, Danijel; Manić, I.; Prijić, Aneta; Djorić-Veljković, S.; Davidović, V.; Stojadinović, N.; Prijić, Z.; Golubović, S.

doi:10.1088/0268-1242/30/10/105009

Cited by 15 publications

(11 citation statements)

References 43 publications

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“…2, NBT stress caused negative threshold voltage shifts ΔV T of 0.28-0.3 V in virgin devices. The observed results can be explained by means of the standard reaction-diffusion (RD) model, which includes reactions involving holes at the Si − SiO 2 interface and in the oxide near interface, accompanied by the release of hydrogen species and their transport through the oxide [25], [26], [31]- [33]. Briefly, a high electric field at elevated temperature in the presence of holes may cause dissociation of weak Si-H bonds at the interface…”

Section: Resultsmentioning

confidence: 99%

“…However, in practice, p-channel power VDMOSFETs are more likely to operate in the dynamic regime than in the static one. Keeping in mind that NBTI effects in dynamically stressed devices are less pronounced [23], [26], it can be concluded that in practical operation, p-channel VDMOSFETs will be less degraded. Under the assumption that high temperature at least does not increase their radiationinduced threshold voltage shift (a decrease of positive oxide charge due to annealing and eventual increase in the density of switching traps would be compensated in p-channel devices), their radiation tolerance level (for defined failure criteria) will be increased.…”

Section: Resultsmentioning

confidence: 99%

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NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors

Davidović

Danković

Ilić

et al. 2016

IEEE Trans. Nucl. Sci.

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In this paper, we report the results of consecutive irradiation and negative bias temperature (NBT) stress experiments performed on p-channel power vertical double-diffused metal-oxide semiconductor transistors. The purpose is to examine the effects of a specific kind of stress in devices previously subjected to the other kind of stress, as well as to assess if possible the behavior of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to a further increase of negative threshold voltage shift due to additional build-up of both oxide trapped charge and interface traps. NBT stress effects in previously irradiated devices may, however, depend on gate bias applied during irradiation and on the total dose received: in the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress seems to lead to further device degradation, whereas in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress seems to have a positive role since it practically anneals a part of radiation-induced degradation.Index Terms-Interface traps, irradiation effects, negative bias temperature instability (NBTI), oxide traps, power devices, thermal annealing, threshold voltage shift, VDMOSFET.

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Section: Resultsmentioning

confidence: 99%

Section: Resultsmentioning

confidence: 99%

NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors

Davidović

Danković

Ilić

et al. 2016

IEEE Trans. Nucl. Sci.

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“…Experiments were done at two different temperatures (150 °C and 175 °C) and values of threshold voltage shifts are obtained. Our ear-lier experiments included testing devices under many different conditions in terms of both gate voltage and temperature [9][10][11][12][13]. Experimental results are given in Figure 1.…”

Section: Methodsmentioning

confidence: 99%

“…Despite notable scale down in the device dimensions, ultra-thick gate oxide reliability studies are still of significance because of broad use of MOS technology. Taking this into consideration, our earlier papers were dealing with NBTI in p-channel power vertical double diffused MOS (VDMOS) transistors [6,[8][9][10][11][12][13]. Their reliability has been investigated under various stress conditions, such as irradiation, high electric field, NBTI, NBTI under low magnetic field, and NBTI and irradiation [13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

Modeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Method

Mitrović¹,

Danković²,

Ranđelović³

et al. 2020

Informacije MIDEM

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Negative bias temperature instability (NBTI) is a phenomenon commonly observed in p-channel metal-oxide semiconductor (MOS) devices simultaneously exposed to elevated temperature and negative gate voltage. This paper studies threshold voltage shift under static stress associated with the NBT stress induced buildup of both interface traps and oxide trapped charge in the commercial p-channel power VDMOSFETs IRF9520, with the goal to design an electrical model. Change of threshold voltage follow power law t n , where parameter n is different depending on the stressing phase and stressing conditions. Two modeling circuits are proposed and modeling circuit elements values are analyzed. Values of modeling circuits elements are calculated using least square method approximation conducted on obtained experimental results. Modeling results of both circuits are compared with the measured results and then further discussed.

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“…In many of these applications devices may be subjected to stress or harsh environment conditions. Accordingly, investigation of their reliability and related effects is of high importance [1][2][3][4][5][6][7][8][9][10][11].…”

Section: Development Of Advanced Electronic Industry Is Based On Combmentioning

confidence: 99%

NBT stress and radiation related degradation and underlying mechanisms in power VDMOSFETs

et al. 2018

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In this paper we provide an overview of instabilities observed in commercial power VDMOSFETs subjected to irradiation, NBT stress, and to consecutive exposure to them. The results have indicated that irradiation of previously NBT stressed devices leads to additional threshold voltage shift, while NBT stress effects in previously irradiated devices depend on the gate bias applied during irradiation and on the total dose received. This points to the importance of the order of applied stresses, indicating that for proper insight into the prediction of device behaviour not only harsh conditions, but also the order of exposure have to be considered. It has also been shown that changes in the densities of oxide trapped charge and interface traps during spontaneous recovery after each of applied stresses can be significant, thus leading to additional instability, even though the threshold voltage seems to remain stable, pointing to the need for clarifying the responsible mechanisms.

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Negative bias temperature instability in p-channel power VDMOSFETs: recoverable versus permanent degradation

Cited by 15 publications

References 43 publications

NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors

NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors

Modeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Method

NBT stress and radiation related degradation and underlying mechanisms in power VDMOSFETs

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