NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors

Abstract

In this paper, we report the results of consecutive irradiation and negative bias temperature (NBT) stress experiments performed on p-channel power vertical double-diffused metal-oxide semiconductor transistors. The purpose is to examine the effects of a specific kind of stress in devices previously subjected to the other kind of stress, as well as to assess if possible the behavior of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to a further increase of negative threshold voltage shift due to additional build-up of both oxide trapped charge and interface traps. NBT stress effects in previously irradiated devices may, however, depend on gate bias applied during irradiation and on the total dose received: in the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress seems to lead to further device degradation, whereas in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress seems to have a positive role since it practically anneals a part of radiation-induced degradation.Index Terms-Interface traps, irradiation effects, negative bias temperature instability (NBTI), oxide traps, power devices, thermal annealing, threshold voltage shift, VDMOSFET.

NBT stress and radiation related degradation and underlying mechanisms in power VDMOSFETs

“…In the case of zero bias applied, the value of V T was the lowest, while at gate bias applied of 10 V it was significantly more pronounced. At the same V T was somewhat more pronounced in the case of positive bias applied (V G =+10 V) than at negative bias applied (V G =-10 V) [11].…”

“…In many of these applications devices may be subjected to stress or harsh environment conditions. Accordingly, investigation of their reliability and related effects is of high importance [1][2][3][4][5][6][7][8][9][10][11].…”

“…Behaviour of V T in p-channel power VDMOSFETs (IRF9520) during the NBT stress-irradiation experiment[11]. Behaviour of V T in p-channel power VDMOSFETs (IRF9520) during the irradiation-NBT stress experiment[11].…”

“…Behaviour of V T in p-channel power VDMOSFETs (IRF9520) during the NBT stress-irradiation experiment[11]. Behaviour of V T in p-channel power VDMOSFETs (IRF9520) during the irradiation-NBT stress experiment[11]. Behaviours of N ot and N it in p-channel power VDMOSFETs (IRF9520) during the NBT stress-irradiation experiment[60].…”

Modeling of Static Negative Bias Temperature Stressing in p-channel VDMOSFETs using Least Square Method

“…Taking this into consideration, our earlier papers were dealing with NBTI in p-channel power vertical double diffused MOS (VDMOS) transistors [6,[8][9][10][11][12][13]. Their reliability has been investigated under various stress conditions, such as irradiation, high electric field, NBTI, NBTI under low magnetic field, and NBTI and irradiation [13][14][15][16]. NBTI is critical for normal operation of power MOS-FETs since they are routinely operated at high current and voltage levels, which lead to both increased gate oxide fields and self-heating, thus favor NBTI.…”