Near-threshold sequential circuits using Improved Clocked Adiabatic Logic in 45nm CMOS processes

Ultra-low power m-sequence code generator for body sensor node applications

“…Operating the digital circuits within the region of sub-threshold voltage is an extreme case of voltage scaling. It has previously been observed that the minimum power consumption can be achieved by operating the circuit in the sub-threshold region [6,7]. Although the circuit switching speed might be slower at this region, however, it remains acceptable for medium performance and low power applications such as wireless sensors and biomedical applications.…”

International Journal of Electronics and Telecommunications

“…VER the last four decades, enrichments in research are being used to obtain a design optimization in the logic circuit to achieve minimum-energy point (MEP). However, circuit performance becomes an issue, it needs to come out of minimum-energy point in order to achieve a significant improvement in high performance [1]. Nowadays, researchers are targeting a unique design under the lower technologies to optimize energy and the speed, a pareto-optimal design curve for optimized operating point (OOP) is as shown in Fig.…”