NBTI degradation effect on advanced-process 45nm high-k PMOSFETs with geometric and process variations

Effects of Gate Stack Structural and Process Defectivity on High-kDielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

“…The test bed p-MOSFET devices with high- k /SiO 2 gate stacks simulated in this study are based on the foundry-standard 32 nm CMOS process. The fabrication process incorporates shallow trench isolation, deposition of high- k dielectrics with metal gate, stress engineering using epi-SiGe pockets, silicidation, and dual-stress liner [ 17 , 21 ]. The fabrication process flow used in this work is presented in Figure 1 .…”

“…To examine the effects of gate geometrics on NBTI, we follow an earlier study [ 21 ] by varying the physical layer thickness of the HfO 2 dielectric layer and the SiO 2 IL. The thickness of each deposited stack layer is within the range of nominal thickness shown in Figure 3 [ 21 , 22 ]. This study aims to account for the contribution of the hole trap to the NBTI degradation effect, whereas the earlier work explains only the interface trap generation in characterizing NBTI effects.…”

NBTI degradation with optimized I<inf>D</inf>-V<inf>G</inf> sweep for wafer fabrication monitoring

“…Under negatively bias in nominal operating condition at (moderately) high temperature, pMOSFETs experienced parametric shift whose dependence on stress time closely follow a power-law [2][3]. Though apparently small over short times, this progressive parametric shift can, over several years, lead the device to fail the design specifications.…”

Defects evolution involving interface dispersion approaches in high-k/metal-gate deep-submicron CMOS

“…Such benchmarks require aggressive junction-depth scaling for higher drive current with simultaneous stringent control of short-channel effects (SCE) [3][4][5]. Accurate prediction of lateral dopant distribution and activation has been a persistent concern for the diffusion less annealing [6][7][8], in addition to maximize device performance with fewer defects.…”

“…Accurate prediction of lateral dopant distribution and activation has been a persistent concern for the diffusion less annealing [6][7][8], in addition to maximize device performance with fewer defects. The major threat to the reliability of deep submicron CMOS circuits evolved from the positive charge formations within gate dielectric and the generation of permanent degradation of generated interface states [2][3][4][5][6][7][8][9]. For pMOSFETs, the negative bias temperature instability (NBTI) is the main concern [10-12] and a framework will be proposed for the defects.…”