Scaled down CMOS transistors are prone to degra dation and process variation. This necessitates a transistor model that provides an insight into the internal dependencies between these two crucial effects. Models for modern transistors and their degradation behavior are hardly attachable. This paper proposes a modified BSIM6 model which includes degradation due to BTl and HCI and in addition process variations. The application of this method is demonstrated on the basis of a single MOSFET and an inverter stage. The results can be used in the grn/1d work flow or for yield estimation on circuit level.