Nanoscale High-k Dielectrics for Junctionless Nanowire Transistor for Drain Current Analysis

Pravin, J. Charles; Prajoon, P.; Nesamania, Flavia Princess; Srikesh, G.; Kumar, Prashant; Nirmal, D.

doi:10.1007/s11664-018-6075-2

Cited by 18 publications

(7 citation statements)

References 37 publications

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“…In our previous work, the SM SNS GAATFT structure was validated and compared with different dielectrics. The result is shown in [13] and among the compared dielectrics HfO2 produces a better performance and [14,15] also supports this.…”

Section: Device Structuresupporting

confidence: 61%

Simulation and Performance Analysis of a Triple-material Gate GAA SNSTFT

Sampson¹,

Sivakumar²,

Velmurugan³

2020

J. Nano- Electron. Phys.

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A Stacked Nano Sheet Gate All Around Thin Film Transistor (SNS GAATFT) with Triple Material (TM) has been proposed in this paper. The TM of the Thin Film Transistor (TFT) is varied by applying three different work functions (WFs) by having different gate materials being used. The transistor considered here for implementation is a p-channel device. The analysis has been carried out using the physical model: temperature-dependent carrier transport model (DD). Mobility Model (MM) includes the effects of doping concentration and electric field, Bandgap Narrowing Model (BNM) and Shockley-Read-Hall recombination Model (SRM) are for carrier lifetime. Synopsys Sentaurus TCAD has been used for the simulation of the proposed model and thus analyzing its characteristics. The characteristics of the proposed TM have been compared to those of the previously proposed Single Material (SM) SNS GAATFT model. For the proposed model, the first and third WFs were kept constant while the WF of the middle region varied between the first and third WFs. The output characteristics analyzed proved a better result for WF values closest to the third WF. Thus, a higher value of the middle WF was used in determining the different characteristics. From the characteristics it can be analyzed that due to varying electric potentials on the gate terminal due to varying WF, the influence of high-speed moving electron is reduced from the source side, and this helps in improving the carrier transport efficiency and thus, it is clear, this, in turn, helps in lowering the hot carrier effects. The comparison result shows that drain current in a TM is found to be almost 4 times higher than that of a SM model which shows better improvement in ION current.

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Section: Device Structuresupporting

confidence: 61%

Simulation and Performance Analysis of a Triple-material Gate GAA SNSTFT

Sampson¹,

Sivakumar²,

Velmurugan³

2020

J. Nano- Electron. Phys.

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“…HfO 2 shows to be a worthy dielectric in terms of Of-state current and gives suitable switching of the device. Consequently, improving the device I ON /I OFF ratio [10].…”

Section: Previous Workmentioning

confidence: 99%

Study ofImpact of HfO2gate oxide on the Electrical Characteristics of Nanowire Junction lessTransistor

Gital¹,

Sule²,

Adamu³

et al. 2022

IJASRE

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This paper proposes hafnium (IV) oxide (HfO2) as gate oxide material of the nanowire junctionless transistor (NJT) to replace the conventional silicon dioxide (SiO2). Leakage current usually increased due to an increase of tunneling of electronsin SiO2transistor when the thickness oxide (tox) of the gate material is below 2nm. The main advantages of HfO2is high dielectric constant k of 20 to 25 which is almost 6 times than that of SiO2. Similarly, HfO2has an energy band gap of 5.3 to 5.7eV. As a result, low leakage current and short channel effects (SCEs) was experienced. An increased in the gate capacitance of the device leads to improve the performance of the device without affecting the enhanced leakage current. All these was achieved by designing and simulating the device using the SDE tools of Sentaurus TCAD. Electrical characteristics was extracted using the Sdevice tools of the software. The performance was significantly increased to approximately 1010using HfO2material

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“…One of the key approaches discussed in literature to obtain good channel electrostatics has been the aggressive reduction of the Effective Oxide Thickness (EOT), thus enhancing the transverse electric field through the use of a High-k material in the gate stack. Due to being thermodynamically stable compared to other High-k dielectrics [7], Hf O 2 has emerged as one of the leading candidates to be used as a High-k material in gate stack. In order to obtain improved device performance at shorter channel lengths, it is important to scale the Effective Oxide thickness (EOT) to less than 1 nm, which is possible through scaling of a High-K gate stack comprising of a High-K gate oxide, such as Hf O 2 , and the SiO 2 layer below it.…”

Section: Introductionmentioning

confidence: 99%

A Negative Capacitance Partially Junction-less Bulk MOSFET with Hysteresis Free Behavior and Improved Performance

Kansal¹,

Medury²

2022

Preprint

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<div>Despite the use of High-k gate stacks, poor channel electrostatics at short channel lengths has limited the applicability of conventional Bulk MOSFETs. With the use of Ferroelectric materials in the gate stack, enhanced transverse (gate) electric field has the potential to enable greater scalability, which needs to be further explored in the context of planar Bulk MOSFETs. In this paper, we firstly present the design of an optimized N-channel Partially Junction-less Bulk MOSFET with a view to suppressing various leakage mechanisms, while also taking channel quantization effects into account. Through detailed process simulations, the process steps required to achieve this device design are determined, thus providing a more practical appraisal of the feasibility of the device. We then identify the thickness of the Ferroelectric layer over the existing gate stack with a view to achieve steep sub-threshold slope (SS) while simultaneously ensuring hysteresis-free characteristics, including enhanced Analog as well as Digital performance of the device.</div><div><br></div>

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Nanoscale High-k Dielectrics for Junctionless Nanowire Transistor for Drain Current Analysis

Cited by 18 publications

References 37 publications

Simulation and Performance Analysis of a Triple-material Gate GAA SNSTFT

Simulation and Performance Analysis of a Triple-material Gate GAA SNSTFT

Study ofImpact of HfO2gate oxide on the Electrical Characteristics of Nanowire Junction lessTransistor

A Negative Capacitance Partially Junction-less Bulk MOSFET with Hysteresis Free Behavior and Improved Performance

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