A Negative Capacitance Partially Junction-less Bulk MOSFET with Hysteresis Free Behavior and Improved Performance

Abstract

<div>Despite the use of High-k gate stacks, poor channel electrostatics at short channel lengths has limited the applicability of conventional Bulk MOSFETs. With the use of Ferroelectric materials in the gate stack, enhanced transverse (gate) electric field has the potential to enable greater scalability, which needs to be further explored in the context of planar Bulk MOSFETs. In this paper, we firstly present the design of an optimized N-channel Partially Junction-less Bulk MOSFET with a view to suppressing various leakage mechanisms, while also taking channel quantization effects into account. Through detailed process simulations, the process steps required to achieve this device design are determined, thus providing a more practical appraisal of the feasibility of the device. We then identify the thickness of the Ferroelectric layer over the existing gate stack with a view to achieve steep sub-threshold slope (SS) while simultaneously ensuring hysteresis-free characteristics, including enhanced Analog as well as Digital performance of the device.</div><div><br></div>