Nanomagnetic logic design approach for area and speed efficient adder using ferromagnetically coupled fixed input majority gate

Abstract

In this letter, we introduce the magnetic quantum-dot cellular automata (MQCA) based area and speed efficient design approach for nanomagnetic full adder implementation. We exploited the physical properties of three input MQCA majority gate (MG), where the fixed input of the MG is coupled ferromagnetically to one of the primary input operands. Subsequently we propose a design methodology, mapping logic and micromagnetic software implementation, validation of the binary full adder architecture built using two–three inputs MQCA MGs. In addition, we also analyzed our proposed design for switching errors to ensure bit stability and reliability. Our proposed design leads to ∼36%–69% reduction in the number of nanomagnets, ∼50%–75% reduction in the number of clock cycles and ∼33%–50% reduction in the number of MG operations required for the binary full adder implementation compared to the state of art designs.

A novel and reliable interlayer exchange coupled nanomagnetic universal logic gate design

“…We have used the 3D OOMMF software [17] for the universal NAND/NOR simulations. OOMMF is widely used simulation tool developed by National Institute of Standards and Technology and it has been observed that for simulations performed in OOMMF, there is credible correlation between the simulation and experimental results [29][30][31][32][33][34][35]. This software uses a finite difference grid with rectangular cells.…”

Dipole coupled magnetic quantum-dot cellular automata-based efficient approximate nanomagnetic subtractor and adder design approach

“…Fixed input of the three-inputs majority gate coupled to its primary input operands, antiferromagnetically and ferromagnetically are referred here as MG and FMG [27], respectively, (cf figures 1(a), (b)). We propose the APN subtractor design using only one majority gate (MG or FMG) and the outputs borrow-out (B o ), difference (D) are computed as defined by equation (1) and its circuit representation as illustrated in figure 1(c).…”

“…To achieve runtime reconfigurability (RR), nanomagnets with variable aspect ratio (NVA) requires a varying field to aid state transitions. Leveraging the advantage of this phenomenon, we built the design as illustrated in figures 2(a), (b) with such NVA in a single layout configured dynamically in runtime as opposed to state-of-the-art approaches [26,27,31]. This layout is represented as RR APN subtractor Design B.…”

“…As part of the arithmetic circuit design using MQCA, Varga et al and Li et al proposed the full adder designs [23][24][25]. Recently Sivasubramani et al proposed a nanomagnetic adder design by exploiting SP hybrid anisotropy [26] and further proposed the mapping logic thus enhancing its efficiency in terms of area and speed using a ferromagnetically coupled fixed input majority gate (FMG) [27]. On the other hand, the intrinsic energy minimization nature and the non-volatility of nanomagnets aids the operation of MQCA-based NML devices at ultra-low power [1][2][3][4][5][6] in comparison to its CMOS counterpart enabling an energy efficient system design.…”

Proposal of Global Strain Clocking Scheme for Majority Logic Gate

“…The basic circuit of CMOS technology is phase inverter, while the basic circuit of NNLD technology is majority logic gate [12]- [15]. How to achieve high-speed lower energy consumption clocking scheme of majority logic gate are problems to be solved urgently now.…”