A novel and reliable interlayer exchange coupled nanomagnetic universal logic gate design

Abstract

In this paper, we propose an interlayer exchange coupling (IEC) based 3D universal NAND/NOR gate design methodology for the reliable and robust implementation of nanomagnetic logic design as compared to the state-of-the art architectures. Owing to stronger coupling scheme as compared to the conventional dipole coupling, the random flip of the states of the nanomagnets (i.e. the soft error) is reduced resulting in greater scalability and better data retention at the deep sub-micron level. Results obtained from Object Oriented Micromagnetic Framework micromagnetic simulation show even at a Curie temperature of the nanomagnets coupled through IEC, the logic function works properly as opposed to dipole coupled nanomagnets which fails at 5 K when scaled down to sub 50 nm. Contemplating the fabrication challenges, the robustness of the IEC design was studied for structural defects, positional misalignment, shape, and size variations. This proposed 3D universal gate design methodology benefits from the miniaturization of nanomagnets as well as reduces the effect of thermally induced errors resulting in opening up a new perspective for nanomagnet based design in magneto-logic devices.

Interlayer exchange couple based reliable and robust 3-input adder design methodology

“…interaction is short range (so there are no long-range parasitic couplings) and may be scaled to smaller volumes before temperature fluctuations make the device unstable [47]. It was shown in [33] that at 5 K for dipole couple nanomagnets scaled to sub 30 nm could not show universal logic gate operations whereas IEC even at 1073 K (Curie temperature) performed accurate operations. Thus, it is expected that dipole couple nanomagnets will have lesser stability as compared to IEC.…”

“…Motivated by the contribution of [27,31,32], authors recently introduced the concept of first time ever universal logic gate design in [33] using the concept of IEC that showed the prospect of designing arithmetic circuits using IEC in the domain of NML. The prior art has the IEC based NAND/ NOR logic gate, but it does not have any adder logic.…”