Nanoimprint system development and status for high-volume semiconductor manufacturing

Abstract

Imprint lithography has been shown to be an effective technique for replication of nano-scale features. Jet and Flash* Imprint Lithography (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate.Criteria specific to any lithographic process for the semiconductor industry include overlay, throughput and defectivity. The purpose of this paper is to describe the technology advancements made overlay, throughput and defectivity and to introduce the FPA-1200NZ2C cluster system designed for high volume manufacturing of semiconductor devices. in the reduction of particle adders in an imprint tool and introduce the new mask replication tool that will enable the fabrication of replica masks with added residual image placement errors suitable for memory devices with half pitches smaller than 15nm.Overlay results better than 5nm 3sigma have been demonstrated. To further enhance overlay, wafer chucks with improved flatness have been implemented to reduce distortion at the wafer edge. To address higher order corrections, a two part solution is discussed. An array of piezo actuators can be applied to enable linear corrections. Additional reductions in distortion can then be addressed by the local heating of a wafer field.The NZ2C cluster platform for high volume manufacturing is also discussed. System development continues this year with a target for introduction later in 2016. The first application is likely to be NAND Flash memory, and eventual use for DRAM and logic devices as both overlay and defectivity improve. *Jet and Flash Imprint Lithography and J-FIL are trademarks of Molecular Imprints Inc.

Promising Lithography Techniques for Next-Generation Logic Devices

“…To accelerate this technology adoption, recently CEA-Leti and EV Group initiated a new program called INSPIRE to diversify the NIL applications beyond semiconductors [68]. Canon also designs nanoimprint lithography tools by collaborating with other vendors and the end users [69].…”

Metrology and inspection required for next generation lithography

“…Among the wide variety of NIL technologies, jet and flash imprint (J-FIL) is the most suitable for IC fabrication for which high productivity and high yield are required. [16][17][18] Figure 1 shows the J-FIL process. Resist is selectively applied by an inkjet to an imprinting field whose size is almost the same as that of an exposure field of a conventional optical scanner (∼26 × 33 mm 2 ), and then a patterned mask (template) is directly contacted to the field with UV exposure.…”

Nanoimprint System for High Volume Semiconductor Manufacturing; Requirement for Resist Materials

“…In the figure below, spread time is tracked over several years as drop volume is reduced from 35 pL to 1.0 pL. Fluid spread time is reduced almost two orders of magnitude from 100 seconds to only 1.5 seconds [16].…”