NAND flash memory device with ground plane in buried oxide for reduced short channel effects and improved data retention

Bohara, Pooja; Vishvakarma, Santosh Kumar

doi:10.1007/s10825-018-01298-9

Cited by 2 publications

(1 citation statement)

References 28 publications

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“…As the nonvolatile memory market grows rapidly, a lot of research has been reported to improve the device performance and reliability. Especially, 3D silicon-oxide-nitride-oxidesilicon (SONOS) flash memory structure has been suggested to overcome the physical limitation in scaling down the feature size of the existing 2D structure [1][2][3][4][5]. Representative ones are the Stacked Memory Array Transistor (SMArT) by SK Hynix, the Pipe Bit Cost Scalable (P-BiCs) by Kioxia, and Terabit Cell Array Transistor (TCAT) by Samsung.…”

Section: Introductionmentioning

confidence: 99%

Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory

Jeong

Sung

et al. 2021

Micromachines

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In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with the number of interface traps and the data retention properties are deteriorated in the device with underlying poly-Si channel which can be serious problem in gate-last 3D NAND flash memory architecture. To improve the memory performance, high pressure deuterium (D2) annealing is suggested as a low-temperature process and the program window and threshold voltage shift in data retention mode is compared before and after the D2 annealing. The suggested curing is found to be effective in improving the device reliability.

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