N and P type top‐gate microcrystalline silicon TFTs processed at low temperature (T < 200 °C) on the same glass substrate

Abstract

Low temperature deposited RF‐PECVD undoped, arsenic and boron doped μc‐Si:H films are used to fabricate the N‐type and P‐type TFTs on the same glass substrate. The transistors have a coplanar top gate configuration and a silicon nitride as gate insulator. The 50 nm thin μc‐Si:H active layer showed a thermal activation energy of the conductivity of 0.57 eV and a crystalline volume fraction of 70%. The arsenic and boron doped μc‐Si:H source/drain contact layers showed a conductivity at room temperature of 5 S/cm and 2.5 S/cm respectively. These TFTs showed a field effect mobility of 0.3 cm2/V.s for electrons and 0.2 cm2/V.s for holes and an (ION/IOFF) current ratio of 107. These results show the possibility to produce CMIS (Complementary Metal Insulator Semiconductor) inverter with silicon nitride as gate insulator at very low temperature compatible with foreign substrates such as flexible plastics or textiles. (© 2010 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

(Invited) Nanocrystalline Silicon Thin Film Transistors

“…In top-gate structures, a-SiO x :H or a-SiN x :H gate dielectrics have been used. Thus far, high field effect mobility has only been achieved in TFTs with a-SiO x :H. Reported mobilities are in the range of 11−450 cm 2 /Vs and 0.5−2 cm 2 /Vs for a-SiO x :H and a-SiN x :H gate dielectrics, respectively (1,(6)(7)(8)(9)(10)(11)(12)(13)(14)(15). Hence, a-SiO x :H is the preferred dielectric for top-gate configuration, as it is for LTPS transistors.…”

“…Hence, a-SiO x :H is the preferred dielectric for top-gate configuration, as it is for LTPS transistors. Although a-SiO x :H forms a good interface with nc-Si that results in a low interface state density and hence high mobility, its bulk insulating quality is poor (1,13). On the other hand, a-SiN x :H forms a low quality interface with nc-Si that leading to high charge trapping at the interface and hence to a low mobility, although its bulk insulating property is very good.…”

Behavior of the parameters of microcrystalline silicon TFTs under mechanical strain

“…The choice of µc-Si:H material is mainly due to being more stable than most of similar materials deposited at low temperature [amorphous silicon,…]. It offers in addition the possibility to produce both N-type and P-type transistors [5][6] and therefore to develop CMOS devices.…”

Electrical and Mechanical Behaviors of Microcrystalline TFTs Deposited on PEN

“…Microcrystalline silicon is chosen for its high potential to produce both N-type and P-type transistors and then CMOS devices. Then we used this µc-Si:H films to fabricate N-type and Ptype on glass substrate with a maximum process temperature of 180°C (3)(4). In this paper, we realize the transfer on PEN substrate of the technology of coplanar Top-Gate N-type microcrystalline silicon TFTs.…”