Mushroom-free selective epitaxial growth of Si, SiGe and SiGe:B raised sources and drains

“…It is usually performed at 750 • C, 20 Torr with a SiH 2 Cl 2 + HCl chemistry, in order to be fully selective versus SiO 2 (isolation between transistors) and SiN (sidewall spacers and hard masks on top of gate stacks). 1,2 The situation is more complex in forthcoming 14 nm technology node devices. Heavily in-situ boron-doped SiGe:B Raised Sources and Drains (RSDs) will have to be used for p-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and heavily in-situ phosphorousdoped Si:P or Si 1-y C y :P RSDs are required for n-type MOSFETs.…”

mentioning

confidence: 99%

Atmospheric Pressure Selective Epitaxial Growth of Heavily In Situ Phosphorous-Doped Si(:C) Raised Sources and Drains

Hartmann

Aubin

Barraud

et al. 2016

ECS J. Solid State Sci. Technol.

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We have developed an innovative atmospheric pressure process for the selective co-flow deposition of Si(C):P Raised Sources and Drains (RSDs) at 700°C–800°C. Layers of Si:P were grown with SiH2Cl2, HCl and a PH3 1% in H2 bottle (with no dependence on growth temperature) resulting in a Si:P growth rate that increased as the PH3 mass-flow increased, together with a P+ ion concentration that reached 7 × 1019 cm−3. For even higher phosphine flows, we have switched to PH3 5% in H2 bottles and studied the growth kinetics and n-type doping of Si at 700°C. The Si:P growth rate increased, stabilized then decreased (which is most likely due to surface poisoning) as the PH3 mass-flow increased. This was associated with a sharp increase then a stabilization at nearly 1020 cm−3 of the P+ ion concentration. The resulting Si:P layers were single crystalline and slightly rough. Full selectivity versus SiO2 (isolation) and SiN sidewall spacers was achieved on patterned wafers with this heavily chlorinated chemistry. Finally, we have evaluated the feasibility of adding SiCH6 to the gaseous mixture to obtain SiC:P layers. The substitutional C concentration was rather small (at most 0.55%). Meanwhile, the resistivity was at first stable then increased, while the SiC:P growth rate monotonously decreased as the SiCH6 mass-flow went up.

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“…Devices have been fabricated at CEA-LETI, starting from Silicon-On-Insulator (SOI) wafers with 145nm buried oxide thickness (tBOX) and using a replacement metal gate (RMG) process to obtain a gate stack composed by HfO2/TiN/W, resulting in effective oxide thickness (EOT) of 1.15nm. Each level has a 10nm thick undoped Si channel and both levels are attached by common metal gate and Si0.7Ge0.3:B raised source/drain (B doping level in the order of few 10 20 cm −3 [13]). The transistors have been fabricated in multi finger structures with 50 fins in parallel and channel length (L) of 100nm.…”

Section: A Vertically Stacked Nwsmentioning

confidence: 99%

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

Paz

Cassé

Barraud

et al. 2018

Solid-State Electronics

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This work proposes a new method for dissociating both channel conductions of two levels vertically stacked inversion mode nanowires (NWs) composed by a Gate-All-Around (GAA) level on top of an Ω-gate level. The proposed methodology is based on experimental measurements of the total drain current (IDS) varying the back gate bias (VB), aiming the extraction of carriers' mobility of each level separately. The methodology consists of three main steps and accounts for VB influence on mobility. The behavior of non-stacked Ω-gate NWs are also discussed varying VB through experimental measurements and tridimensional numerical simulations in order to sustain proposed expressions of mobility dependence on VB for the bottom level of the stacked structure. Lower mobility was obtained for GAA in comparison to Ω-gate. The procedure was validated for a wide range of VB and up to 150°C. Similar temperature dependence of mobility was observed for both Ω-gate and GAA levels.

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Mushroom-free selective epitaxial growth of Si, SiGe and SiGe:B raised sources and drains

Cited by 15 publications

References 24 publications

Patterning of silicon nitride for CMOS gate spacer technology. II. Impact of subsilicon surface carbon implantation on epitaxial regrowth

Patterning of silicon nitride for CMOS gate spacer technology. II. Impact of subsilicon surface carbon implantation on epitaxial regrowth

Atmospheric Pressure Selective Epitaxial Growth of Heavily In Situ Phosphorous-Doped Si(:C) Raised Sources and Drains

Methodology to separate channel conductions of two level vertically stacked SOI nanowire MOSFETs

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