Multivoltage Floorplan Design

Ma, Qiang; Young, Evangeline F. Y.

doi:10.1109/tcad.2010.2042895

Cited by 32 publications

(61 citation statements)

References 11 publications

(22 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, the placement size m × n at the cell-level is usually too large to employ DP directly in practical 2 This is a simple approximation to reduce computational complexity, and its impact is reflected in our experimental results. applications.…”

Section: Coarse Grid Reconstructionmentioning

confidence: 96%

“…Motivated by the fact that individual blocks of a circuit can have timing/power characteristics unique from the rest of the design, the concept of multi-supply voltage (MSV) design was introduced to trade off power consumption and performance, and has attracted lots of interests from both academia and industry [1][2][3][4][5][6][7][8][9]. In MSV designs, circuits are partitioned into multiple "voltage islands" and each island operates at a specified supply voltage that satisfies its performance requirement.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Post-placement voltage island generation for timing-speculative circuits

Yuan

Sun

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

View full text Add to dashboard Cite

Region-based multi-supply voltage (MSV) design, by which circuits are partitioned into multiple "voltage islands" and each island operates at a supply voltage that meets its own performance requirement, is an effective technique to tradeoff power and performance. Different from conventional voltage island generation techniques that work in a conservative manner to guarantee "always correct" computation, in this work, we investigate the MSV design problem for timingspeculative circuits, which achieves high energy-efficiency by allowing the occurrence of infrequent timing errors and correcting them online. A novel algorithm based on dynamic programming is developed to tackle this problem. Experimental results on various benchmark circuits demonstrate the effectiveness of the proposed methodology.

show abstract

Section: Coarse Grid Reconstructionmentioning

confidence: 96%

Section: Introductionmentioning

confidence: 99%

Post-placement voltage island generation for timing-speculative circuits

Yuan

Sun

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

View full text Add to dashboard Cite

show abstract

“…The values of the parameters α, β and γ can be assigned by the designer [3] or be set using random walks at the beginning of the annealing process [12]. In regards to the inclusion of fixed-outline floorplan constraint, sequence pairs that do not meet the chip width/height are initially considered to be legal solution.…”

Section: B Cost Functionmentioning

confidence: 99%

“…In all the previous work [2]- [9], power optimization and floorplanning has been considered as two distinct steps. Simultaneous voltage assignment, voltage island generation and floorplanning using Normalized Polish Expression was first considered in [12]. However, island partitioning and voltage assignment is performed for every candidate floorplan.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Sequence pair based voltage island floorplanning

Sengupta

Veneris

Wilton

et al. 2011

2011 International Green Computing Conference and Workshops

View full text Add to dashboard Cite

Abstract-In the nanometer era of VLSI design, high power consumption is considered to be a "show-stopper" for many applications. Voltage Island design has emerged as a popular method for addressing this issue. This technique requires multiple supply voltages on the same chip with blocks assigned to different supply voltages. Implementation challenges force blocks with similar supply voltages to be placed contiguous to one another, thereby creating "islands". Classical floorplanners assume a single supply voltage in the entire SoC and thus require additional design steps to realize voltage islands. In this paper we present a new floorplanning algorithm based on the sequence pair representation that can floorplan blocks in the form of islands. Given the possible supply voltage choices for each block, the floorplanner simultaneously attempts to reduce power and area of the chip. Our floorplanner integrates the tasks of assigning blocks to different supply voltages and the placing of the blocks in the chip. Compared to previous work, the proposed floorplanner on average reduces the area overhead of the chip by 13.5% with 34% runtime improvement. Additionally we explore the tradeoff between power and area for different floorplan solutions.

show abstract

Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning

Chu

Xia

Wang

et al. 2015

Circuit Theory & Apps

View full text Add to dashboard Cite

Multi-voltage techniques are being developed to improve power savings by providing lower supply voltages for noncritical blocks under the performance constraint. However, the resulted lower voltage drop noise margin brings serious obstacles in power/ground (P/G) network design of the wire-bonding package. For voltage drop optimization, both block and power pad positions are important factors that need to be considered. Traditional multi-voltage floorplanning methods use rough estimation to evaluate the P/G network resource without considering the locations of power pads. To remedy this deficiency, in this paper, an efficient voltage drops aware power pad assignment (PPA) method is proposed, and it is further integrated into a floorplanning algorithm. We first present a fast PPA method for each power domain by the spring model. Then, to evaluate voltage drops during floorplanning iterations, the weighted distance from the blocks to the power pads is adopted as an optimization objective instead of time-consuming matrix computation. Experimental results on Gigascale System Research Center (GSRC) benchmark circuits indicate that the proposed method generates an optimized placement of power pads and floorplanning of blocks with high efficiency.decoupling capacitors configuration to alleviate the power delivery noise [12,13]. However, those techniques are implemented only when the floorplan or placement is ready. With exploding design complexity, it is necessary to consider voltage drop issues in the early design cycle [14][15][16][17]. Once the voltage drops aware floorplan is obtained, the detailed P/G network design can be performed in the subsequent placement and routing stages that consider Steiner tree construction and electromigration issues [18,19].It is reported that 5% of voltage decrease may cause the circuit performance slowdown up to 15% or more [20]. Hence, designers typically limit the voltage drops within 10% of the supply voltage to guarantee faultless operation [21]. Lower supply voltage indicates that lower noise margins or smaller voltage drops are permitted on the P/G network [22]. For instance, 1.5-V supply voltages permit 150-mV voltage drop while 1.0-V supply voltages only allow 100-mV voltage drop. Compared with single-voltage SoC, the voltage drop constraints present more challenges for the P/G network design of the multi-voltage SoC. First, from a low-power perspective, a VI with a larger area and a lower supply voltage is preferred during the VI generation process. However, the permitted ultra-low voltage drops make the P/G network hard to design. Second, power pads are located at the periphery of the chip for wire-bonding package. Locations of power pads affect both the timing and voltage drops [23]. Although multiple power pads for each VI can leverage the voltage drops, it may not be practical because the power pads must compete with other signal I/Os under the limited pad resource. Thus, it is vital to consider voltage drops in P/G network design for multi-voltage SoC. Related workConsid...

show abstract

Multivoltage Floorplan Design

Cited by 32 publications

References 11 publications

Post-placement voltage island generation for timing-speculative circuits

Post-placement voltage island generation for timing-speculative circuits

Sequence pair based voltage island floorplanning

Efficient power pad assignment for multi‐voltage SoC and its application in floorplanning

Contact Info

Product

Resources

About