Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator

Marinella, Matthew; Agarwal, Sapan; Hsia, Alexander H.; Richter, Isaac; Jacobs-Gedrim, Robin; Niroula, John; Plimpton, Steven J.; Ïpek, Engin; James, Conrad D.

doi:10.1109/jetcas.2018.2796379

Cited by 138 publications

(104 citation statements)

References 25 publications

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“…[6,17,[20][21][22] Achieving lower memristor conductances lowers the voltage drop on the interconnect wires, allowing lower computing current and larger array sizes. Operating in lower conductances is not only needed to reduce overall power consumption but also essential to improve the computing accuracy.…”

mentioning

confidence: 99%

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Sheng

Graves

Kumar

et al. 2019

Adv Elect Materials

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in computing accelerators compared to high density storage-class memory, it is frequently important in computing applications to program multiple bits of information within every device by achieving many distinct conductance levels, while keeping the operating currents lower especially at the high conductance states. Operating in lower conductances is not only needed to reduce overall power consumption but also essential to improve the computing accuracy. For example, in analog matrix-vector multiplication, voltage drops across metal interconnect lines cause computational errors and, therefore, the memristor array size must be limited. [6,17,[20][21][22] Achieving lower memristor conductances lowers the voltage drop on the interconnect wires, allowing lower computing current and larger array sizes. This further benefits the energy and area efficiency by amortizing the costs of anolog to digital converters (ADC) required in the circuit. [4] However, existing demonstrations have a narrow dynamic range and achieving multiple low conductance levels is challenging. A larger ratio between the high and low conductances (on/off ratio) helps in achieving more distinct programmable low conductance levels. In addition, memristors are required to be integrated with CMOS circuits in many such applications. For instance, a 1-transistor-1-memristor (1T1M) combination provides in situ current compliance through gate voltage modulation so that the memristor can be programmed in an analog manner. [12,16,25] This brings another challenge: compatibility of memristor and CMOS. This includes not only material and fabrication compatibility, but also CMOS performance meeting the memristor operating requirements as both continue size scaling. Thus, it is essential to demonstrate all the aforementioned properties in nanometer-scale memristors repeatedly and reproducibly.Among various forms of memristors, oxide memristors outperform others by possessing the advantages of lower programming and computing energy, favorable scaling in cell size, [10,11,30] and CMOS-compatibility in materials and fabrication. Recently, many reports demonstrated enouraging results using multiple-bits in HfO x , TaO x , and other oxide memristors for neuromorphic computing applications, [23][24][25]31,32] making these highly promising if CMOS-integrated nanoscale devices can be demonstrated wtih wide dynamic range and promising yield numbers.Using memristors, such as oxide and phase change resistive switches, as tunable resistors to construct analog computing hardware accelerators is gaining keen attention. Such accelerators have demonstrated the potential to significantly outperform digital computers in highly relevant applications such as machine learning and image processing. However, improvements in device-level performance of memristors, including reducing power consumption and high current-induced metal migration in interconnects, need continued developments. Nanoscaling and complementary metal-oxide semiconductor (CMOS) integration are also of significant ...

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confidence: 99%

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Sheng

Graves

Kumar

et al. 2019

Adv Elect Materials

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“…A synaptic operation (synaptic event) is understood in nonspiking networks as an operation of multiplication of an input signal by a weight, i.e., "multiplyand-accumulate" (MAC). However in spiking networks, a synaptic even is mostly understood as "A spike event is a synaptic operation evoked when one action potential is transmitted through 21 one synapse" according to [44]. There may be multiple spikes required to fire a neuron, i.e.…”

Section: Chip-level Benchmarksmentioning

confidence: 99%

“…The Eyeriss simulation tool focuses on accelerators for DNN [20]. The CrossSim simulator has similar capabilities [21].Benchmarking of a variety of devices, including beyond-CMOS ones, has been done in an approach similar to ours, but for one type of neural networks only, cellular neural networks (CeNN) [22]. Various estimates of time and energy of operation for certain types of digital and analog devices have been done previously [23,24,25,26].…”

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confidence: 99%

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Benchmarking Delay and Energy of Neural Inference Circuits

Nikonov

Young

2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Numerous neural network circuits and architectures are presently under active research for application to artificial intelligence and machine learning. Their physical performance metrics (area, time, energy) are estimated. Various types of neural networks (artificial, cellular, spiking, and oscillator) are implemented with multiple CMOS and beyond-CMOS (spintronic, ferroelectric, resistive memory) devices. A consistent and transparent methodology is proposed and used to benchmark this comprehensive set of options across several application cases. Promising architecture/device combinations are identified.In the last few years, AI/ML achieved prominent successes, especially related to deep neural networks (DNN) [7] and convolutional neural networks (CoNN). ML has enabled a revolutionary improvement in the accuracy of image, pattern, and facial recognition, including 2 the treatment of 'big data' online. More demand for neural computing is emerging in robotic control, autonomous vehicles, drones, etc.One of the main concerns on the minds of developers of AI computing systems is the same as for traditional computing: the power consumption in the chips. The history of traditional computing shows that the commercial success of computing devices and architectures is predicated largely on their physical performanceareal density, speed of operation, and consumed energy as benchmarked in [8,9]. These ultimately translate into processing throughput and consumed power of the chips, which are of utmost importance to the user. A fair comparison between the published neural network implementations is difficult due to the difference in the process technology generation, the network architectures, and computing workloads.The main purpose of the paper is to establish a methodology for comparing various neural network hardware approaches and to understand the trends revealed through its development. In doing that we strive to adhere to the following principles: a) general: wide scope of technologies, devices and circuits; b) transparent: simple analytics more important than precise simulations; c) uniform: consistent inputs and assumptions across multiple types of hardware; d) transparent: all models used are described and the code is available [10] to the reader for verification.Let us differentiate this work from the existing body of literature. We do not aim to give a literature review, and refer the reader to the excellent review papers in the neuromorphic hardware field [11,12] which do not attempt to quantitatively compare prior works, as we do in this paper. Oftentimes benchmarking refers to comparing various algorithms for an application mainly based on their accuracy and with little reference to hardware implementation, e.g. [13]. In contrast, we compare different types of hardware implementing the same algorithm and focusing on its energy consumption and performance.The discussion of neural networks in the numerous papers currently being published remains at the architecture level. For example, the accuracy of recognition...

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“…[23][24][25][26][27] For instance, if every device, say along a row, were identical and perfectly linear in conductance versus number of pulses, then it is fairly straightforward to determine the number of pulses required on G + , G − , g + , and g − to program the set of target weights. Several previous works acknowledge the importance of parallelized weight programming, which is nontrivial in the presence of significant variability in NVM conductance versus pulse characteristics.…”

Section: Introductionmentioning

confidence: 99%

Weight Programming in DNN Analog Hardware Accelerators in the Presence of NVM Variability

Mackin

Tsai

Ambrogio

et al. 2019

Adv Elect Materials

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large and unavoidable time and energy penalties for data transport between memory and computational blocks-the so-called "von Neumann" bottleneck.Analog hardware accelerators for deep learning can avoid this bottleneck by performing MAC operations in memory using a crossbar array structure. [5][6][7] In these crossbar arrays, nonvolatile memory (NVM) elements are used to encode synaptic weights. This was recently shown capable of 280× speedup in per area throughput while also providing 100× enhancement in per area energy efficiency over state-of-the-art GPUs. [8] While the benefits of speed are readily appreciated, enhancement in energy efficiency can be a powerful driver of purchasing decisions in the data center space as well. [9][10][11][12] Crossbar arrays have been implemented using a variety of analog NVM elements, including resistive RAM (ReRAM), [13,14] conductive-bridging RAM (CBRAM), [15] flash, [16][17][18][19][20] and phase-change memory (PCM). [21,22] However, most NVM device candidates exhibit varying extents of nonideal behavior, including limited resistance contrast, significant nonlinearity in conductance change, as well as strong asymmetry in bidirectional programming. At the application level, this manifests into neural network accuracies that are significantly lower than software-based approaches. Many of these nonidealities, however, can be addressed to an extent through device and circuit-level engineering. One key idea is multiple conductances of varying significance (Figure 1a), where each synaptic weight is distributed across at least two conductance pairs using W = F(G + − G − ) + (g + − g − ). For instance, during training, such a PCM cell could be paired with a capacitive cell to combine complementary features of both and relax the overall device requirements on PCM. [8] In such a scheme, the majority of DNN weight tuning can occur on a linear but volatile 3T1C memory structure, with periodic but infrequent transfer to the PCM cell for nonvolatile storage. Row-(or column-)wise weight transfer also arises in ex situ training and other training variants. Since PCM is subject to the previously mentioned nonidealities, this weight transfer is best performed with a closed-loop iterative tuning procedure with multiple write-plus-read-verify steps to achieve the overall target weight. To avoid performance degradation, particularly during training, NVM programming Crossbar arrays of nonvolatile memory (NVM) can potentially accelerate development of deep neural networks (DNNs) by implementing crucial multiply-accumulate (MAC) operations at the location of data. Effective weight-programming procedures can both minimize the performance impact during training and reduce the down time for inference, where new parameter sets may need to be loaded. Simultaneous weight programming along an entire dimension (e.g., row or column) of a crossbar array in the context of forward inference and training is shown to be important. A framework for determining the optimal hardware conditions in which to program w...

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Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator

Cited by 138 publications

References 25 publications

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Low‐Conductance and Multilevel CMOS‐Integrated Nanoscale Oxide Memristors

Benchmarking Delay and Energy of Neural Inference Circuits

Weight Programming in DNN Analog Hardware Accelerators in the Presence of NVM Variability

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