Multiple stopping criteria and high-precision EMD architecture implementation for Hilbert-Huang transform

Abstract

In this work, a multiple stopping criteria and highprecision empirical mode decomposition (EMD) hardware architecture implementation is proposed for Hilbert-Huang transform (HHT) in biomedical signal processing. The proposed architecture can support multiple stopping criteria including the constant criteria, the SD criteria and the ratio criteria. The 38-bit floating point precision is adopted in this work to support 10 IMF components with enough accuracy. The off-chip memory architecture is adopted to increase the processing capacity. By the pipelined cubic spline coefficient unit (PCSCU), the computation time can be reduced. The proposed EMD hardware architecture is implemented in TSMC 90 nm CMOS process with the core area of 4.47 mm 2 at the operating frequency of 40 MHz. The post-layout simulation result shows that our work with the constant criterion can speed up the performance 50.4 times compared to the software computation on a single core of ARM11 for 2K data size breathing signals.

FPGA and ASIC realisation of EMD algorithm for real‐time signal processing

“…Power dissipation in our case is 299.59 mW, which is higher than the power dissipation of [22], but in our case, VDD = 1.8 V and clock rate = 50 MHz. Whereas VDD = 1 V and clock rate = 40 MHz in case of [22]. Both FPGA and ASIC implementation is done for the EMD with STI and MOVAVG, but for EMD with CSI we have done only the FPGA implementation.…”

“…Table 5, shows the comparison among the proposed method and some existing methods. Here, we have proposed an FPGA‐ and ASIC‐based implementation of EMD, whereas in [7–9, 12, 17, 22], it is either FPGA‐ or ASIC‐based. Our proposed design (case 1;) can work with a sampling rate of 25 MHz which is higher than the sample rate of any other EMD implementation (a different version of EMD is proposed in [17]).…”

“…16) of the proposed EMD is done with a core area of , using SCL 180 nm technology library. Which is less as compared to the core area which is proposed in [22], they used TSMC 90 nm technology library. Power dissipation in our case is 299.59 mW, which is higher than the power dissipation of [22], but in our case, VDD = 1.8 V and clock rate = 50 MHz.…”

“…Which is less as compared to the core area which is proposed in [22], they used TSMC 90 nm technology library. Power dissipation in our case is 299.59 mW, which is higher than the power dissipation of [22], but in our case, VDD = 1.8 V and clock rate = 50 MHz. Whereas VDD = 1 V and clock rate = 40 MHz in case of [22].…”

An efficient hardware realization of EMD for real‐time signal processing applications

“…The authors proposed an ASIC design for EMD having different stopping criteria. 17 The authors made an effort to reduce the computation time of EMD by using pipeline technique in the CSI's coefficient calculation. However, the method needed 11.494 ms to process 2000 data samples.…”