An efficient hardware realization of EMD for real‐time signal processing applications

Abstract

This paper presents a field-programmable gate array (FPGA) and applicationspecific integrated circuit (ASIC) based design for the real-time implementation of empirical mode decomposition (EMD) algorithm. Here, at the beginning, register-transfer-level (RTL) design of EMD algorithm is developed in the form of verilog-HDL code. Then, simulation-based testing of the RTL design is done. In this paper, two envelope computation methods are proposed: one using linear Bezier curve (LBC) and the other using cubic spline interpolation (CSI). For ASIC, the verilog-HDL code of EMD is synthesized using Genus tool of Cadence using SCL 180-nm technology library and Innovus tool of Cadence is used for the layout design. The core area of the proposed EMD ASIC is 1.16 mm 2 and can be operated at 62.5 MHz clock rate. The developed FPGA-based EMD architecture can be operated at 50 MHz clock rate and up to 50 MHz sampling rate. Here, an effort is also made to classify the normal and seizure/ictal electroencephalogram (EEG) signals, which are used as an input to EMD, with the help of a support vector machine (SVM). The classification accuracy obtained is above 99%, and here, MATLAB is used for feature calculation and classification purposes. K E Y W O R D S application specific integrated circuit (ASIC), empirical mode decomposition (EMD), field programmable gate array (FPGA), support vector machine (SVM)

Field‐programmable gate array‐based design for real‐time computation of ensemble empirical mode decomposition

“…Many FPGA-based designs were proposed for EMD, 15,[17][18][19][20] whereas in Chen et al, 22 a semi FPGA-based design for EEMD was proposed. In Table 7, we have presented the comparison of our design with existing designs in respect of FPGA used, envelope computation, clock rate, sampling frequency, and execution time.…”

“…But, our proposed EMD and EEMD designs with CSI is effective for real-time processing also. The two main reasons responsible for more execution time in Das et al 19 are the dividers, and different types of FPGA were used. In this present work, we have replaced all the division operations with the multiplications, and division by power of 2 values are replaced with shift operations.…”

“…Their proposed designed was operated at a clock rate and sampling frequency of 46.44 MHz. In Das and Pradhan, 19 an FPGA-and ASIC-based design of EMD using fixed-point arithmetic was proposed. The FPGA-and ASIC-based designs of EMD have an operating clock frequency of 50 and 62.5 MHz, respectively.…”

Comparison of Empirical Mode Decomposition and Singular Spectrum Analysis for Quick and Robust Detection of Aerodynamic Instabilities in Centrifugal Compressors

“…It allows benchmarking two methods and provides estimation of the timescale needed for applying each of them, providing some understanding of whether the methods have a potential to be used in real time. However, it might be assumed that if the times of acquisition and processing are similar when using PC, the implementation using FPGA solutions will be at least equally quick [39,40].…”