Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint

Li, Katherine Shu-Min; Hung, Yu-Chen; Huang, Jr-Yang

doi:10.1109/ats.2009.60

Cited by 2 publications

(2 citation statements)

References 32 publications

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“…Many methods have been proposed to compress test data, compact test responses, reduce test application time and test power by using new scan architectures [Banerjee et al 2007;Xiang 2009, 2010;Li 2010;Sinanoglu 2008;Sinanoglu and Orailoglu 2002;Tzeng and Huang 2009;Wang et al 2010;Xiang et al 2007;Xiang and Chen 2011]. Considering the limitations of the compatibility scan flip-flops, an approximate compatibility scheme was proposed to compress test data, compact test responses, and reduce test application time in Banerjee et al [2007].…”

Section: Related Workmentioning

confidence: 98%

“…A new scan chain partitioning scheme in Wang et al [2010] was proposed to improve the compressibility of the existent coding-based test compression methods by properly filling the don't cares. Recently, a routing-driven scan tree synthesis method was proposed in Li [2010] to compress test data, reduce test application time, and compact test responses. An interconnectdriven layout-aware multiple scan tree synthesis methodology for 3-D ICs was recently proposed to reduce test data volume and test application cost in Li and Liao [2012].…”

Section: Related Workmentioning

confidence: 99%

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A thermal-driven test application scheme for pre-bond and post-bond scan testing of three-dimensional ICs

Xiang

Shen

2014

J. Emerg. Technol. Comput. Syst.

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The three-dimensional (3-D) technology offers a new solution to the increasing density of integrated circuits (ICs). In this work, we propose novel scan architectures for 3-D IC pre-bond and post-bond testing by considering the interconnection overhead of through-silicon-vias (TSVs). Since hotspots in 3-D ICs often cause performance and reliability issues, we also develop different test ordering schemes for prebond and postbond testing to avoid applying test vectors that could worsen the temperature distribution. Experimental results show that the peak temperature can be lowered by 20% with the 3-D scan tree architecture. When combined with the test ordering scheme, the 3-D scan tree can further reduce peak temperature by over 30%. ACM Reference Format:Dong Xiang and Kele Shen. 2014. A thermal-driven test application scheme for pre-bond and post-bond scan testing of three-dimensional ICs.

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